fix(gen-verilog): size struct and uN entry ports by one rule (#5904) - #5955
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An on_comb parameter becomes a module port only when its width can be
derived exactly, and the port is as wide as the input the generated
function declares for it (FR-001). One definition decides this --
VerilogCodegen::entry_port_width -- and the entry-points census calls it
instead of keeping a private is_sized_primitive list.
- Struct ports: a struct whose fields are all strictly sized is a port of
the summed field width (no `_ => 32` default). The width is checked
against packed_width_in on the same struct map, so port == function
input. Nested structs, slices and f32/f64 stay refused.
- uN / iN for 1 <= N <= 128 are N bits in ports and type_to_width;
type_is_signed accepts iN.
- A refusal is reported on stderr as
`t27c gen-verilog: ENTRY POINT REFUSED -- <param>: <type>`; the in-file
comment and the exit status are unchanged.
- A parameterless on_comb is called with W530's 1'b0 placeholder
(`on_comb()` failed iverilog). Reachable now that `-> u1` is sized;
also fixes d_full_path.t27 and d_static_one.t27, which already failed
iverilog on master.
Measurements (release t27c, 1174 specs):
- ternary_mac + on_comb(acc: i32, a: i8, w: TernaryWeight):
NO DATA PORTS 0, `input wire [7:0] w` 1, yosys 222 cells.
- led_off_test.t27: ENTRY POINT REFUSED 0, `function [31:0] on_comb` 0;
iverilog rc 0, yosys 0 cells (result tied to 1).
- slice spec: stderr refusal lines 1, exit 0.
- Corpus gen-verilog diff vs master: 8 specs, stderr and exit codes
identical for every spec.
- Odd widths: igla/training/low_bit_ternary (i2 -> signed [1:0]),
numeric/formats (u5, u4 parameters), numeric/gf4 (u4),
tri/crypto/base64 (u6 locals), tri/utils/utf8 (u21).
- led_off_test no longer refused (u1); d_full_path and d_static_one
call on_comb(1'b0).
- No corpus on_comb takes a struct. Corpus specs refused: 1 -> 0.
- t27c entry-points: FORCED_ROOT 3 -> 7, FORCED_ROOT_WIDE 33 -> 29,
FORCED_SCALAR 22 -> 25, FORCED_WIDE 55 -> 52; named-type blockers
105 -> 84; HAS_ENTRY 95, NOPARSE 12, NO_CANDIDATE 469 unchanged.
- Seals: 9 files for the 5 odd-width specs resealed with
`t27c seal <spec> --save`; check_seal_coverage.py OK (1314 hold).
- FROZEN_HASH resealed with `t27c frozen-digest`.
- cargo test -p t27c: 2797 passed, 2 failed (the 2 known baseline
failures), vs baseline 2789 passed; +6 tests in
tests/verilog_struct_entry_ports.rs, +2 entry_points unit tests.
gen/verilog/ is a stale snapshot (last regenerated at #1399), so it was
not regenerated here.
Closes #5904
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Closes #5904 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This was referenced Oct 4, 2026
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gHashTag#5955 merged; bring the branch onto master. compiler.rs is unchanged by master, so FROZEN_HASH still matches. Closes gHashTag#5963 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Summary
t27c gen-verilogturned anon_combparameter into a module port only for a short list of primitive types, so a spec whose datapath takes a struct (or an odd-widthuN) got a module with no data ports and synthesized to zero logic. This PR gives the port decision one owner and widens it to every type whose width can be derived exactly.VerilogCodegen::entry_port_widthdecides whether a parameter becomes a port and how wide it is. The entry-points census (t27c entry-points) now calls it instead of keeping its ownis_sized_primitivelist, so the census and the generator cannot disagree._ => 32default). The width is checked againstpacked_width_inon the same struct map, so the port is exactly as wide as the input the generated function declares. Nested structs, slices andf32/f64stay refused.uN/iNfor 1 <= N <= 128 are N bits in ports and intype_to_width;type_is_signedacceptsiN.t27c gen-verilog: ENTRY POINT REFUSED -- <param>: <type>. The in-file comment and the exit status are unchanged.on_combis called with the W5301'b0placeholder;on_comb()failed iverilog. This also fixesd_full_path.t27andd_static_one.t27, which already failed iverilog on master.Acceptance (from #5904)
ternary_mac+on_comb(acc: i32, a: i8, w: TernaryWeight):NO DATA PORTSinput wire [7:0] wportssynthcellsled_off_test.t27: ENTRY POINT REFUSEDis_sized_primitiveinbootstrap/src(code)Corpus effect (1174 specs, release t27c)
gen-verilogoutput changed for 8 specs; stderr and exit status identical for every spec.igla/training/low_bit_ternary(i2->signed [1:0]),numeric/formats(u5,u4),numeric/gf4(u4),tri/crypto/base64(u6locals),tri/utils/utf8(u21).led_off_testno longer refused (u1);d_full_pathandd_static_onecallon_comb(1'b0).on_combtakes a struct today, so the struct path is covered by the new tests.t27c entry-points: FORCED_ROOT 3 -> 7, FORCED_ROOT_WIDE 33 -> 29, FORCED_SCALAR 22 -> 25, FORCED_WIDE 55 -> 52; named-type blockers 105 -> 84; HAS_ENTRY 95, NOPARSE 12, NO_CANDIDATE 469 unchanged.Seals
t27c seal <spec> --save;check_seal_coverage.pyOK.bootstrap/stage0/FROZEN_HASHmoved to the new SHA-256 ofbootstrap/src/compiler.rs.gen/verilog/is a stale snapshot (last regenerated at conformance: promote gf256 -> strict SW-bitexact (last rung, 75/0/8) #1399) and is not regenerated here (L2).Tests
cargo test -p t27c: 2797 passed, 2 failed, vs 2789 passed on the base. The 2 failures are the known baseline failures and fail identically without this change.bootstrap/tests/verilog_struct_entry_ports.rs(6 tests) and 2 unit tests inentry_points.rs.Not in this PR
on_clockhandler's parameters are refused but the module still has output ports, no refusal comment is written into the file (stderr still reports it).Closes #5904. Part of #5905.
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