fix(gen-verilog): name a refused on_clock entry point in the .v file (#5963) by gHashTag · Pull Request #5967 · gHashTag/t27

gHashTag · 2026-10-04T08:23:47Z

Summary

t27c gen-verilog wrote the in-file // ENTRY POINT REFUSED comment only inside the // NO DATA PORTS branch. An on_clock whose parameter has no derivable width, in a module that still exposes a var as an output port, took the other branch: the .v file said nothing about the refusal (stderr has reported it since #5955). The comment now comes from one helper, VerilogCodegen::write_entry_refusal_comment, called whenever an entry point is refused, for on_comb and on_clock alike. No second copy of the message text.

Before / after

module slice_clock;
var acc : u8 = 0
fn on_clock(xs: []u8) { acc = acc + 1; }

Before (head of #5955): stderr t27c gen-verilog: ENTRY POINT REFUSED -- xs: []u8, and the file had no refusal comment:

    output wire        ready,
    output reg [7:0] acc
);

    // -------------------------------------------------------

After: same stderr, same exit code (0), and the file says why xs has no port:

    output reg [7:0] acc
);
// ENTRY POINT REFUSED -- a parameter or return has no derivable width:
//     xs: []u8
// `[N]T` is accepted (N*width(T) is arithmetic). A slice has no length in
// the type; `f64` has a size but not an encoding. Neither is guessed here.

Corpus

gen-verilog over all 1183 specs under specs/, baseline binary (#5955 head) vs this branch: 0 files differ in stdout, stderr or exit code (1163 exit 0, 19 exit 1 on both sides). No corpus spec has a refused entry point, so the change is visible only to new specs. No seals touched; FROZEN_HASH updated for compiler.rs.

Tests

Three new tests in bootstrap/tests/verilog_struct_entry_ports.rs:

a refused on_clock slice parameter is named exactly once in the file and once on stderr, and the acc output port remains (fails on the baseline binary);
the on_clock and on_comb refusal comment blocks are identical, and the port-less on_comb case still writes it once;
negative control: an accepted on_clock (x: u8) writes no refusal.

cargo test -p t27c --release --test 'verilog_*': 43 passed, 0 failed.

Closes #5963
Part of #5905

🤖 Generated with Claude Code

…5963) The ENTRY POINT REFUSED comment lived inside the NO DATA PORTS branch, so an on_clock whose parameter had no derivable width but whose module still had a var output port wrote nothing into the file (stderr reported it since #5904). Move the comment into write_entry_refusal_comment and call it whenever an entry point is refused, for on_comb and on_clock alike. Corpus gen-verilog is byte-identical (no corpus spec is refused). FROZEN_HASH updated for compiler.rs. Closes #5963 Part of #5905 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

#5955 merged; bring the branch onto master. compiler.rs is unchanged by master, so FROZEN_HASH still matches. Closes #5963 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

github-actions · 2026-10-04T08:35:11Z

PR Dashboard

Generated at: 2026-10-04 08:35:03 UTC

ci: every check is a .t27 card -- schema, generator, three pilots (P1 of #5933) #5970 ci: every check is a .t27 card -- schema, generator, three pilots (P1 of #5933) | Created: 2026-10-04 | Updated: 2026-10-04 | 27 failing / 31 total
feat(trinity): re-pin the S01 manifest to gHashTag/trinity#1333 and add the test.brain card #5969 feat(trinity): re-pin the S01 manifest to gHashTag/trinity#1333 and add the test.brain card | Created: 2026-10-04 | Updated: 2026-10-04 | 24 failing / 31 total
fix(gen-verilog): name a refused on_clock entry point in the .v file (#5963) #5967 fix(gen-verilog): name a refused on_clock entry point in the .v file (#5963) | Created: 2026-10-04 | Updated: 2026-10-04 | 17 failing / 34 total
spec(trinity): a capability card for the brain region tests, one ahead of the pin (Closes #5953) #5965 spec(trinity): a capability card for the brain region tests, one ahead of the pin (Closes #5953) | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 32 total
fix(t27c): refuse a Rust match block the parser kept as text; rewrite nine as switch #5964 fix(t27c): refuse a Rust match block the parser kept as text; rewrite nine as switch | Created: 2026-10-04 | Updated: 2026-10-04 | 11 failing / 39 total
ci(fpga): fpga-bitstream is an Arty A7-100T smoke build -- never offer it for the Wukong #5960 ci(fpga): fpga-bitstream is an Arty A7-100T smoke build -- never offer it for the Wukong | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 39 total
ci: remove the NotebookLM hooks and workflows -- the sync is a stub, the gate checks a tracked constant #5958 ci: remove the NotebookLM hooks and workflows -- the sync is a stub, the gate checks a tracked constant | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl #5956 Port gHashTag/trinity:fpga/openxc7-synth/blink_minimal.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bl | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 31 total
ci: remove the NOW gate -- nothing asks for a docs/now entry any more #5951 ci: remove the NOW gate -- nothing asks for a docs/now entry any more | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 39 total
fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) #5948 fpga: elaboration ratchet back to 176 -- ternary_isa (W459), uart (spec), adapter (NEW-clean) (Closes #5908) | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 46 total
fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) #5947 fix(t27c): refuse macro calls and typeless fields; rewrite eight Markdown specs (#5923) | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 42 total
Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 #5946 Port gHashTag/trinity:src/background_agent/main.zig (Zig, 1 function) to specs/port/trinity/src/background_agent/main.t2 | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
spec(split-reel): v9 -- each voice is held to its own slowest measured pace #5932 spec(split-reel): v9 -- each voice is held to its own slowest measured pace | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 32 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to #5926 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/provider-error-classifier.ts (TypeScript, 1 function) to | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 31 total
CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) #5924 CI: spec-guards and emit-bitexact restore master cargo caches; cancel superseded emit-bitexact runs (B25) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 32 total
ring-096 and formats.t27 agree on f32 (Closes #5746) #5921 ring-096 and formats.t27 agree on f32 (Closes #5746) | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 56 total
build(t27c): reqwest on native-tls, drop the aws-lc-sys build #5920 build(t27c): reqwest on native-tls, drop the aws-lc-sys build | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 41 total
fix(rust): preserve writes to by-value parameter bindings #5911 fix(rust): preserve writes to by-value parameter bindings | Created: 2026-10-04 | Updated: 2026-10-04 | 30 failing / 33 total
fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) #5902 fix(t27c): var tuple destructure silences never-mutated Zig locals (Closes #5886) | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 46 total
spec(crm-client-workspace): v6 -- client work carries the client's marks #5893 spec(crm-client-workspace): v6 -- client work carries the client's marks | Created: 2026-10-04 | Updated: 2026-10-04 | 1 failing / 32 total
Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op #5888 Port gHashTag/trios:crates/trios-openclaw/rings/OC-01/src/lib.rs (Rust, 3 functions) to specs/port/trios/crates/trios-op | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o #5887 Port gHashTag/trinity:fpga/openxc7-synth/d_oscillator.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_o | Created: 2026-10-04 | Updated: 2026-10-04 | 5 failing / 35 total
Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 #5883 Port scripts/test-agent-bridge.sh (Shell, 1 function) to specs/port/scripts/test-agent-bridge.t27 | Created: 2026-10-04 | Updated: 2026-10-04 | 2 failing / 35 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to #5879 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/a2a/a2a-liveness.ts (TypeScript, 2 functions) to | Created: 2026-10-04 | Updated: 2026-10-04 | 3 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le #5866 Port gHashTag/trinity:fpga/openxc7-synth/led_both_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/le | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio #5855 Port gHashTag/trios:crates/trios-scarab-types/rings/SR-01/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio | Created: 2026-10-04 | Updated: 2026-10-04 | 4 failing / 35 total
feat(tri pr ready): --why compares what a pre-existing failure printed #5853 feat(tri pr ready): --why compares what a pre-existing failure printed | Created: 2026-10-04 | Updated: 2026-10-04 | 21 failing / 44 total
Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en #5836 Port gHashTag/trinity:src/vibeec/validation_engine.zig (Zig, 3 functions) to specs/port/trinity/src/vibeec/validation_en | Created: 2026-10-03 | Updated: 2026-10-04 | 5 failing / 35 total
feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame #5828 feat(tri): tri harness -- a page measured at 375px and 1024px, every visible frame | Created: 2026-10-03 | Updated: 2026-10-04 | 28 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli #5822 Port gHashTag/trinity:fpga/openxc7-synth/blink_simple.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/bli | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e #5820 Port gHashTag/trinity:fpga/openxc7-synth/uart_echo.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/uart_e | Created: 2026-10-03 | Updated: 2026-10-04 | 4 failing / 35 total
tri: stranded-work finder and cron tick resume card #5787 tri: stranded-work finder and cron tick resume card | Created: 2026-10-03 | Updated: 2026-10-04 | 2 failing / 3 total
Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr #5783 Port gHashTag/trinity:fpga/openxc7-synth/d_srl_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_sr | Created: 2026-10-03 | Updated: 2026-10-04 | 2 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu #5781 Port gHashTag/trinity:fpga/openxc7-synth/d_bufg_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_bu | Created: 2026-10-03 | Updated: 2026-10-04 | 3 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ #5780 Port gHashTag/trinity:fpga/openxc7-synth/led_on_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/led_ | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 36 total
Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) #5778 Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lane-credits.ts (TypeScript, 4 functions) | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 32 total
bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) #5777 bees/merger/publisher: reviewer bee as a service, merger reads discounted checks, publisher heading passes check (Closes #5776) | Created: 2026-10-03 | Updated: 2026-10-04 | 0 failing / 31 total
Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 #5757 Port gHashTag/trinity:fpga/openxc7-synth/d_g22_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_g22 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 35 total
Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t #5756 Port gHashTag/trinity:fpga/openxc7-synth/d_y0_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_y0_t | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 37 total
Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 #5755 Port scripts/tri-issue-create.py (Python, 1 function) to specs/port/scripts/tri-issue-create.t27 | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 37 total
fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) #5745 fix(tri): gates preview reads the PR body the way the issue gate does (Closes #5744) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 42 total
fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) #5732 fix(tri): gates preview asks the contexts the ruleset requires, parse-ratchet among them (Closes #5725) | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 43 total
Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 #5689 Port gHashTag/trinity:fpga/openxc7-synth/d_e21_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d_e21 | Created: 2026-10-03 | Updated: 2026-10-03 | 2 failing / 32 total
spec(automation): kanban-card-chat v7 -- the bee's own log on a running card, live #5680 spec(automation): kanban-card-chat v7 -- the bee's own log on a running card, live | Created: 2026-10-03 | Updated: 2026-10-03 | 5 failing / 32 total
docs(constitution): entrench Article CREDIT and seal it (v1.3) #5667 docs(constitution): entrench Article CREDIT and seal it (v1.3) | Created: 2026-10-03 | Updated: 2026-10-03 | 4 failing / 40 total
specs/port/fpga/verilog/ternary_mac_synth.t27: rewrite w_code_to_mult/product in t27 form (explicit return, element-wise #5664 specs/port/fpga/verilog/ternary_mac_synth.t27: rewrite w_code_to_mult/product in t27 form (explicit return, element-wise | Created: 2026-10-03 | Updated: 2026-10-03 | 1 failing / 36 total
Port gHashTag/trinity:fpga/openxc7-synth/symbiflow_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/ #5663 Port gHashTag/trinity:fpga/openxc7-synth/symbiflow_blink.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/ | Created: 2026-10-03 | Updated: 2026-10-03 | 3 failing / 36 total
docs(igla): re-take the corpus figures on master, 1150 specs (Refs #5497) #5610 docs(igla): re-take the corpus figures on master, 1150 specs (Refs #5497) | Created: 2026-10-02 | Updated: 2026-10-02 | 1 failing / 34 total
The Queen's accept is the merge: dispatch.t27 says so, and its harness measures it #5452 The Queen's accept is the merge: dispatch.t27 says so, and its harness measures it | Created: 2026-10-01 | Updated: 2026-10-02 | 6 failing / 36 total
docs(tri): mark the Solana tri-mining program and depin.prove rewards superseded by mint-on-acceptance (Closes #5412) #5413 docs(tri): mark the Solana tri-mining program and depin.prove rewards superseded by mint-on-acceptance (Closes #5412) | Created: 2026-10-01 | Updated: 2026-10-02 | 6 failing / 32 total

Summary

Status	Count
Total Open PRs	50
PRs with Failing Checks	43
PRs with All Checks Green	7
READY	1
FAILING	43
PENDING	0
NO CHECKS YET	0

These columns do not partition: 1 + 43 + 0 + 0 = 44, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

⚠️ STALE -- sha256(compiler.rs)=f4a1fbade08e != manifest seal=87e5cbd3ad94.
The committed NMSE numbers were certified against an older compiler.rs.
Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

github-actions · 2026-10-04T08:40:36Z

📓 NotebookLM Notebook linked to this PR

Notebook ID: b83263109fb055dc
URL: https://notebooklm.google.com/notebook/b83263109fb055dc

This notebook contains session context, decisions, and artifacts for this work.

gHashTag and others added 2 commits October 4, 2026 15:21

Merge origin/master into claude/verilog-on-clock-refusal-comment

e37b05d

#5955 merged; bring the branch onto master. compiler.rs is unchanged by master, so FROZEN_HASH still matches. Closes #5963 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

github-actions Bot mentioned this pull request Oct 4, 2026

spec(trinity): a capability card for the brain region tests, one ahead of the pin (Closes #5953) #5965

Merged

github-actions Bot mentioned this pull request Oct 4, 2026

feat(trinity): re-pin the S01 manifest to gHashTag/trinity#1333 and add the test.brain card #5969

Closed

github-actions Bot mentioned this pull request Oct 4, 2026

ci: every check is a .t27 card -- schema, generator, three pilots (P1 of #5933) #5970

Open

gHashTag merged commit eeaebdd into master Oct 4, 2026
38 of 40 checks passed

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fix(gen-verilog): name a refused on_clock entry point in the .v file (#5963) - #5967

fix(gen-verilog): name a refused on_clock entry point in the .v file (#5963)#5967
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