widgets: nine more tools from their own .t27 specs, and gatle

[gHashTag]

Closes #1379
Closes #1380
Closes #1381
Closes #1384
Closes #1385
Closes #1386
Closes #1387
Closes #1394
Closes #1396
(epic #1377)

Nine more widget tools for the WIDGETS tab, each a static page at t27.ai/widgets/<id>/ generated from specs/widgets/<id>.t27. Stacked on #1383, rebased onto main after it merged.

widget	tests	hook (from its spec)
bit-autopsy	6	Five bitstreams committed to t27 write the XC7A100T IDCODE; the bench is a 200T. Drop your .bit and see which chip it asks for.
fasm-skyline	5	114803 FASM features in 2148 tiles: 5.23% of an XC7A200T. Drop your own .fasm and watch the design stand up as a city.
synth-smells	5	Paste your yosys log and see the latch you did not mean, the wire nothing drives, and the RAM that became 16 flip-flops.
vcd-wrapped	5	Your testbench toggled clk 585 times and left 4 signals at X all run. Drop your .vcd and see your simulation, wrapped.
fits-on	7	nextpnr said 1% LUTs. That design fits 28 times on a 200T, not 100: type your own LUT count and see which resource runs out first.
stat-card	6	Paste your yosys stat -json, get a card to post and a badge for your README: LUT, FF, DSP, BRAM, marked as a synth count.
lut-depth	4	Our GF16 adder's longest path: 23 cells, 11 of them LUTs. Plain ltp -noff said 27: it walked through two 7-series flip-flops it does not skip.
fsm-sketch	5	Did yosys see your state machine? Drop its fsm_export file or log and see the graph it extracted, or the reason it refused.
gatle	4	Can you out-guess yosys? One real t27 module a day, six guesses at its LUT count. Puzzle #1 cost 1826 LUTs; splitting the range took five.

Found while building

• trinity#1401: gf16_add.v:165 range select.
• t27#6224: 12 specs whose generated Verilog yosys refuses; 8 are non-constant function calls.
• t27#6259: [N]str array size is not checked by the compiler.

{
  "version": 1,
  "head_sha": "59fc1cbf173b670c4d6d605709b387bf743a64f8",
  "summary": "Nine more widget tools generated from their own specs/widgets/<id>.t27, listed in the Queen's WIDGETS tab as kind tool; the gallery now holds 40 widgets and 6 ideas, and gatle is a daily guessing game over real t27 modules.",
  "changes": [
    "Nine specs under specs/widgets/ (bit-autopsy, fasm-skyline, synth-smells, vcd-wrapped, fits-on, stat-card, lut-depth, fsm-sketch, gatle) with 47 test blocks; their tool.js, tool.css, card.png and data files under public/widgets/<id>/.",
    "scripts/widget-data/ gains the scripts that produced each widget's data and card, so every number on a page is reproducible from a named command.",
    "specs/widgets/gallery.t27 lists the nine as tool at the end of their category runs, remaps the asserted indices, and refills the idea shelf with xdc-check and open-flow-check from the competitor sweep.",
    "src/lib/queenWidgets.generated.ts and public/widgets/gallery.t27 regenerated from the gallery spec.",
    "src/data/siliconHistory.ts loses the second gf16_attn exclusion key: #1383 added it while main gained the same key in 3fbafd19b, and the duplicate (TS1117) turned the typecheck ratchet red on main."
  ],
  "tests": [
    {
      "command": "node scripts/widget-pages-from-spec.mjs --check",
      "result": "22 tool pages up to date; spec tests 114, asserts 609, all hold",
      "status": "passed",
      "evidence": "Local run on this branch after rebasing onto main at 8cd27f51c (tri widget check)."
    },
    {
      "command": "node --test scripts/widget-pages-from-spec.test.mjs",
      "result": "3 pass, 0 fail on the rebased branch",
      "status": "passed",
      "evidence": "Local run on this branch."
    },
    {
      "command": "node scripts/widgets-from-spec.mjs --check",
      "result": "40 widgets in 3 categories, 6 ideas not built; spec tests 7, asserts 22, all hold",
      "status": "passed",
      "evidence": "Local run on this branch."
    },
    {
      "command": "npm run typecheck:ratchet (tsc -p tsconfig.app.json)",
      "result": "179 errors across 26 files; baseline 179 across 26; no file gained, siliconHistory.ts back to 0",
      "status": "passed",
      "evidence": "Local run on this branch."
    },
    {
      "command": "tri widget status --repo <this checkout>",
      "result": "22 tools, 0 problems: every tool has spec, page, tool.js, card and no gitignored file",
      "status": "passed",
      "evidence": "Local run of ~/skills/widget-forge/scripts/widget.py status."
    }
  ],
  "limitations": [
    "Widget data are snapshots taken by the scripts under scripts/widget-data/ on the dates their specs name; nothing re-runs them on deploy.",
    "gatle's pool holds 37 of 1682 specs, the ones whose generated Verilog yosys accepts; the rest are filed on t27#6224.",
    "lut-depth and fsm-sketch read yosys output the reader pastes; yosys itself does not run in the browser.",
    "Nothing is posted anywhere; cards are made for the owner to post."
  ],
  "tags": [
    "t27",
    "FPGA",
    "Widgets",
    "QueenBoard"
  ],
  "blog": {
    "title": "Nine more FPGA widgets, and a daily game that asks you to out-guess yosys",
    "summary": "Bitstream autopsy, FASM skyline, synth log smells, VCD wrapped, fits-on, stat card, LUT depth, FSM sketch and gatle: each a static page whose words and numbers live in a .t27 spec with its own tests.",
    "outline": [
      "Bit-autopsy found five committed bitstreams that ask for a 100T while the bench holds a 200T; the page reads the IDCODE straight from the reader's .bit file.",
      "Synth-smells and fsm-sketch turn the yosys log a reader already has into the latch, the undriven wire and the state machine they did not know about.",
      "Gatle is a daily puzzle built from real t27 modules: the reader guesses the LUT count yosys reported, with six tries and a hint after each.",
      "What the builders found on the way: Verilog that yosys refuses, a string size the compiler does not check, and an ltp flag that walks through flip-flops."
    ]
  }
}

🤖 Generated with Claude Code

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Tests: 261/261 passed, 0 leaked
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