Skip to content

fpga/openxc7-synth: tmu.v reads *_wide.mem files that are not committed; tmu_tb fails 0/8 #1393

Description

@gHashTag

Found while building the vcd-wrapped widget (#1385, epic #1377).

What: fpga/openxc7-synth/tmu.v:146 loads $readmemb({MEM_FILE_PREFIX, "_wide.mem"}, bank_mem_wide) -- the single (2*K)-bit "WIDE BRAM" layout. The directory holds only the old per-bank files (tmu_test_w_b00.mem .. tmu_test_w_b15.mem, tmu_w_b{1,2,3}_{up,down}_bNN.mem); no *_wide.mem is committed.

Effect (measured): with Icarus Verilog 12.0,

iverilog -g2012 -s tmu_tb -o sim.vvp fpga/openxc7-synth/tmu_tb.v fpga/openxc7-synth/tmu.v
vvp -n sim.vvp

tmu_tb passes 0 of 8 checks, with X outputs (the weight memory is never loaded). hardware/rtl-root/tmu_tb.v has the same dependency.

Fix options: commit the *_wide.mem files generated from the per-bank files (bank b00 in the low 2 bits, per the comment at tmu.v:138-141), or have the testbench generate them; then rerun tmu_tb and record 8 of 8.

The widget ships this run labelled "fails in this repo" and will be re-recorded when this is fixed.

Other testbenches seen failing in the same sweep (not investigated): tb_hslm_ternary_mac (2 errors, X neurons), embedding_lookup_tb ("FAILED: 2431 errors in 6 tests").

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Projects

    No projects

      Milestone

      No milestone

      Relationships

      None yet

      Development

      No branches or pull requests

      Issue actions