feat(compiler): Zig fork — 7 patches for ternary SIMD (f16 vectors, i2 SIMD, popcount)

[gHashTag]

Zig Compiler Fork for Ternary Architecture

Fork: gHashTag/zig from ziglang/zig

7 Patches (by priority)

#	Feature	Blocks	Complexity	Upstream
1	Vector @floatCast f16↔f32	f16 SIMD matmul (#330)	easy	#16267
2	@Vector(N, i2) optimized	packed ternary SIMD (#333)	medium	—
3	Mixed-width vector ops (i2×f32)	ternary × float	medium	—
4	@popCount for vectors	integer attention (#334)	easy	—
5	Comptime SIMD width detection	auto-tune platform	easy	—
6	@prefetch for slices	safe prefetch API	easy	—
7	Vector asm register constraints	f16 fallback intrinsics	medium	—

Strategy

• Workarounds in Trinity (inline for, asm) work WITHOUT fork
• Fork needed only for native performance (remove workaround overhead)
• Each patch = separate PR to upstream ziglang/zig
• Fork = staging area for our patches until merge upstream

Patch #1: Vector @floatcast

Location: src/Sema.zig → zirFloatCast

Current: blocks @floatcast for vector types with TODO.
Fix: emit LLVM fpext/fptrunc for vector float types (LLVM supports natively).

Checklist

• ci: Bump actions/upload-artifact from 4 to 6 #1 Vector @floatcast f16↔f32
• ci: Bump actions/setup-node from 4 to 6 #2 @vector(N, i2) optimized packed ops
• ci: Bump actions/setup-python from 5 to 6 #3 Mixed-width vector operations (i2 × f32)
• ci: Bump actions/checkout from 4 to 6 #4 @popcount for vectors
• ci: Bump actions/download-artifact from 4 to 7 #5 Comptime SIMD width detection
• deps: Bump @anthropic-ai/sdk from 0.40.1 to 0.72.1 in /vibee-electron #6 @prefetch for slices
• Add Claude Code GitHub Workflow #7 Vector asm register constraints

Related

• feat(hslm): Fully Ternary Transformer — 0 floating point operations #329 (parent epic)
• feat(hslm): [A] f16 SIMD Vectors — branchless matvec with half precision #330 (f16 SIMD), feat(hslm): [D] Ternary Activations — STE quantizer + integer matmul #333 (Ternary Activations), feat(hslm): [E] Ternary Attention — integer scoring + sparse attend #334 (Ternary Attention)

[gHashTag]

Patch #1 Status: @floatcast for f16 vectors

Finding

Good news: Current Zig master (0.15.x) already supports vector @floatCast generically — including f16. The zirFloatCast function in src/Sema.zig (line 10106) handles vectors via sema.coerce (fpext) and .fptrunc (fptrunc) without type restrictions.

However: There were zero tests for f16 vector casts. Only f32↔f64 was tested.

What we did

Branch: feat/vector-float-cast

Added 5 test cases in test/behavior/cast.zig:

1. @Vector(8, f16) → @Vector(8, f32) (fpext)
2. @Vector(8, f32) → @Vector(8, f16) (fptrunc)
3. f16 → f32 → f16 roundtrip
4. @Vector(4, f16) → @Vector(4, f64) (multi-step widening)
5. @Vector(16, f16) 16-wide SIMD (ML workload test)

Impact on Trinity

Since f16 vector @floatcast already works, Issue #330 (f16 SIMD) can proceed immediately without a compiler fork. The inline-for workaround is still useful for older Zig versions, but standard Zig 0.15 handles it natively.

Next: PR to upstream ziglang/zig with test coverage