feat(hslm): [A] f16 SIMD Vectors — branchless matvec with half precision

[gHashTag]

Parent: #329 — Fully Ternary Transformer

Level 0 (no dependencies) | ~200 LOC | Edit: src/hslm/sparse_ternary.zig

Description

Add f16↔f32 SIMD helpers and branchlessMatvecF16 to sparse_ternary.zig. f16 vectors = 2x throughput vs f32 on same SIMD width.

Implementation

• f16↔f32 conversion helpers (inline for workaround until Zig gets vector @floatCast)
• branchlessMatvecF16() — f16 input/output, ternary weights
• Backward pass for f16
• Benchmark: f16 vs f32 throughput comparison

tri CLI

tri hslm benchmark-f16

Tests

• f16↔f32 roundtrip precision
• f16 matvec matches f32 matvec (within f16 tolerance)
• Benchmark output

Blocked by

Nothing (Level 0)

Blocks

• Issue D (Ternary Activations) — benefits from f16 path

[gHashTag]

Consolidated into feat(hslm) epic #329 — Fully Ternary Transformer