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fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) - #7626
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… the Ethernet FCS (Closes #7625) specs/fpga/rgmii.t27 (module fpga_rgmii): RGMII v2.0 timing as test-checked arithmetic: 125 MHz DDR = 1000 Mbps, 8 ns period / 4 ns nibble phase, the 10/100 downshift as SDR (25 MHz / 2.5 MHz, one edge -- DDR at 25 MHz would carry 200 Mbps, the trap the test names), IDELAYE2 tap math from UG471 (78 ps at the 200 MHz reference, 31 taps = 2418 ps; a 2.0 ns shift costs 26 taps, the 4 ns half-period does not fit -- delay elements centre the eye, they do not slip phase), and the Artix-7 fact that ODELAYE2 does not exist outside HP banks. Constants cite their sources; every other number is derived by the tests. No board measurement exists yet -- the header says THEORETICAL and names the boards. specs/fpga/eth_crc.t27 (module fpga_eth_crc): The 802.3 FCS as one spec: reflected 0xEDB88320 step, byte table (every entry re-derived from crc_bit by test table_is_derived), preset/post-xor 0xFFFFFFFF, FCS = one's complement. ORACLE vectors computed with Python 3 zlib.crc32, not transcribed: the published check value 0xcbf43926, one octet, empty, two frames (broadcast/IPv4, slow-protocols/length), and the receiver fact that frame + FCS returns the register to 0xFFFFFFFF. The 0x2144DF1C / 0xDEBB20E3 magic residues belong to other CRC conventions and are deliberately not claimed. Both compile clean through the wasm t27c (typecheckOk, hirOk, 0 errors). Their tests use calls, locals and separated/hex literals, which the in-browser mini-runner cannot execute -- the known trinity#1477 gap; the native runner executes them. Refs gHashTag/trinity#1484 (buses-and-peripherals, module 8) Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
…1484) The Zig reference rejects an array literal longer than its [32]u8 parameter (expected 32 array elements; found 36), which the wasm typecheck accepts -- caught by the t27b corpus run in CI, not by the local check. Every crc_buf literal now carries exactly 32 elements: the first len bytes are the frame, the rest zero padding the loop never reads. All oracle values are unchanged because crc_buf only folds data[0..len]. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
…gs (Closes #7625, Refs trinity#1484) eth_crc.t27 is a self-contained player spec and carries its own hex and CRC bit helpers, like the two specs that already share hex_nibble_of; crc_bits was unique until now. Recorded in the same commit as the specs, per the gate's own instruction. build_tree 5 rides along from the merged master specs. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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…specs join, 2 unexpected passes and 4 moves recorded (Closes #7625, Refs trinity#1484) The master ledger had drifted: 17 specs landed after the last batch bless plus this PR's rgmii and eth_crc. weight_bram and fuzz now fit the frame cap and pass; census, a64 and macho enter as blocked with their reasons. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
…errors (Closes #7625, Refs trinity#1484) CI measured both generated modules at 0 iverilog elaboration errors; the ratchet refuses modules the baseline has never heard of even at zero, so they join the ledger in sorted position. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-07 23:01:06 UTC
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…aster's builtin-plan side plus this PR's 19 unlisted (Closes #7625, Refs trinity#1484) Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This was referenced Oct 7, 2026
…vely Every failing assert compared the RUNNING register against zlib's post-inverted values, off by exactly the final ^ 0xFFFFFFFF, and the receiver test claimed the register returns to its preset after frame+FCS. No 802.3 CRC-32 does: with the FCS appended LSB-first the register settles at the residue 0xDEBB20E3 (zlib view 0x2144DF1C), computed with Python zlib, the oracle the header already names. - FCS is the post-inverted register (the zlib value), sent LSB first: 02 e7 a6 68 for frame A; the old text complemented the FCS itself - vector constants re-pinned to both views; value asserts whose oracle is a zlib value now go through fcs_of - receiver test renamed receiver_residue_is_the_magic, asserts the residue 0xDEBB20E3, frame bytes carry the real FCS - comments inside test bodies moved to top level: a ';' inside a body is a parse error, not a comment (hit twice while editing) - result: 8/8 pass, 0 vacuous, 1 invariant, t27c check clean Refs trinity#1484 Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This was referenced Oct 8, 2026
This was referenced Oct 8, 2026
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PR DashboardGenerated at: 2026-10-08 20:03:01 UTC
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This was referenced Oct 8, 2026
The t27b ledger conflicted with master on its counts. The ledger is now master's entries, plus the entries master does not list yet (this PR's #7625 additions) and this PR's own specs; counts are recounted. Three entries the PR's earlier re-bless held stale (zig_field_syntax, weber_tuning, weight_bram) take master's measurement again, so the cap equals reality (37). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ScHVrGSr6zZUdwkdC8DR9k
This was referenced Oct 8, 2026
The t27b ledger conflicted with master on its counts. The ledger is now master's entries, plus the entries master does not list yet (this PR's #7625 additions) and this PR's own specs; counts are recounted. Three entries the PR's earlier re-bless held stale (zig_field_syntax, weber_tuning, weight_bram) take master's measurement again, so the cap equals reality (37). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01ScHVrGSr6zZUdwkdC8DR9k
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PR DashboardGenerated at: 2026-10-08 23:21:26 UTC
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Merging now, while the head is mergeable. The four required checks are green on b3dc089.
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Supersedes #7615: same content with a clean three-commit history on
fpga/specs-rgmii-eth-crc-1484b(the old branch's root commit predated the issue and failed the L1 commit-reference gate; the API cannot swap a PR head, so the fixed history ships as a new PR).Two new pure-t27 specs the trinity buses-and-peripherals course (gHashTag/trinity#1484, module 8) lists as required:
specs/fpga/rgmii.t27 —
module fpga_rgmiiHAVE_ODELAY == false).specs/fpga/eth_crc.t27 —
module fpga_eth_crctable_is_derivedre-deriving every entry fromcrc_bit, preset/post-xor 0xFFFFFFFF,fcs_of= one's complement.zlib.crc32(real tool, not transcription): check value0xcbf43926, single octet, empty, two frames (broadcast+IPv4 header, slow-protocols+length), and the receiver fact — CRC over frame + FCS returns the register to0xFFFFFFFF.0x2144DF1C/0xDEBB20E3residues belong to other CRC conventions and are deliberately not claimed (the wrong-constant mistake was caught by re-running the tool, see commit).Verification
Both compile clean through the wasm t27c (
typecheckOk: true, hirOk: true, 0 errors). Their tests use calls, locals and separated/hex literals — exactly what the in-browser mini-runner cannot execute (known gap, gHashTag/trinity#1477); the native runner covers them.Refs gHashTag/trinity#1484, Refs gHashTag/trinity#1476
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Closes #7625 (this repo's spec request; the course that consumes them is gHashTag/trinity#1484)