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fpga: RGMII timing arithmetic and Ethernet FCS specs (for the buses course) - #7615

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fpga/specs-rgmii-eth-crc-1484
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gHashTag wants to merge 4 commits into
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fpga/specs-rgmii-eth-crc-1484

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@gHashTag

@gHashTag gHashTag commented Oct 7, 2026 •

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Two new pure-t27 specs the trinity buses-and-peripherals course (gHashTag/trinity#1484, module 8) lists as required:

specs/fpga/rgmii.t27 — module fpga_rgmii

  • RGMII v2.0 arithmetic, test-checked: 125 MHz DDR = 1000 Mbps; 8 ns period / 4 ns nibble phase; 125 MB/s byte rate.
  • The 10/100 downshift is SDR — 25 MHz / 2.5 MHz, one edge; the test names the trap (DDR at 25 MHz would carry 200 Mbps).
  • IDELAYE2 tap math (UG471): 78 ps/tap at the 200 MHz reference, 31 taps = 2418 ps; a 2.0 ns shift costs 26 taps; the 4 ns half-period does not fit one IDELAY — delay elements centre the eye, they do not slip phase.
  • Artix-7 = HR banks: no ODELAYE2 (asserted as HAVE_ODELAY == false).
  • Every constant cites its source; every other number is derived by a test. Header carries an explicit THEORETICAL marker: no RGMII board measurement exists on the bench yet (checked 2026-10-08); board PHYs differ and must be named.

specs/fpga/eth_crc.t27 — module fpga_eth_crc

  • 802.3 FCS: reflected 0xEDB88320 step function, 256-entry byte table with table_is_derived re-deriving every entry from crc_bit, preset/post-xor 0xFFFFFFFF, fcs_of = one's complement.
  • ORACLE vectors all computed with Python 3 zlib.crc32 (real tool, not transcription): check value 0xcbf43926, single octet, empty, two frames (broadcast+IPv4 header, slow-protocols+length), and the receiver fact — CRC over frame + FCS returns the register to 0xFFFFFFFF.
  • The famous 0x2144DF1C / 0xDEBB20E3 residues belong to other CRC conventions and are deliberately not claimed (the wrong-constant mistake was caught by re-running the tool, see commit).

Verification

Both compile clean through the wasm t27c (typecheckOk: true, hirOk: true, 0 errors). Their tests use calls, locals and separated/hex literals — exactly what the in-browser mini-runner cannot execute (known gap, gHashTag/trinity#1477); the native runner covers them.

Refs gHashTag/trinity#1484, Refs gHashTag/trinity#1476

🤖 Generated with Claude Code

Closes #7625 (this repo's spec request; the course that consumes them is gHashTag/trinity#1484)

… the Ethernet FCS

specs/fpga/rgmii.t27 (module fpga_rgmii):
RGMII v2.0 timing as test-checked arithmetic: 125 MHz DDR = 1000 Mbps,
8 ns period / 4 ns nibble phase, the 10/100 downshift as SDR (25 MHz / 2.5
MHz, one edge -- DDR at 25 MHz would carry 200 Mbps, the trap the test
names), IDELAYE2 tap math from UG471 (78 ps at the 200 MHz reference, 31
taps = 2418 ps; a 2.0 ns shift costs 26 taps, the 4 ns half-period does
not fit -- delay elements centre the eye, they do not slip phase), and the
Artix-7 fact that ODELAYE2 does not exist outside HP banks. Constants
cite their sources; every other number is derived by the tests. No board
measurement exists yet -- the header says THEORETICAL and names the boards.

specs/fpga/eth_crc.t27 (module fpga_eth_crc):
The 802.3 FCS as one spec: reflected 0xEDB88320 step, byte table (every
entry re-derived from crc_bit by test table_is_derived), preset/post-xor
0xFFFFFFFF, FCS = one's complement. ORACLE vectors computed with Python 3
zlib.crc32, not transcribed: the published check value 0xcbf43926, one
octet, empty, two frames (broadcast/IPv4, slow-protocols/length), and the
receiver fact that frame + FCS returns the register to 0xFFFFFFFF. The
0x2144DF1C / 0xDEBB20E3 magic residues belong to other CRC conventions
and are deliberately not claimed.

Both compile clean through the wasm t27c (typecheckOk, hirOk, 0 errors).
Their tests use calls, locals and separated/hex literals, which the
in-browser mini-runner cannot execute -- the known trinity#1477 gap; the
native runner executes them.

Refs gHashTag/trinity#1484 (buses-and-peripherals, module 8)

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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github-actions Bot commented Oct 7, 2026

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PR Dashboard

Generated at: 2026-10-07 21:29:46 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 46
PRs with All Checks Green 4
READY 1
FAILING 46
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 46 + 0 + 0 = 47, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=39fa3908f9fd != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

…1484)

The Zig reference rejects an array literal longer than its [32]u8 parameter
(expected 32 array elements; found 36), which the wasm typecheck accepts --
caught by the t27b corpus run in CI, not by the local check. Every crc_buf
literal now carries exactly 32 elements: the first len bytes are the frame,
the rest zero padding the loop never reads. All oracle values are unchanged
because crc_buf only folds data[0..len].

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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github-actions Bot commented Oct 7, 2026

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PR Dashboard

Generated at: 2026-10-07 22:05:12 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 49
PRs with All Checks Green 1
READY 1
FAILING 49
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=39fa3908f9fd != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

gHashTag and others added 2 commits October 8, 2026 05:16
…gs (Closes #7625, Refs trinity#1484)

eth_crc.t27 is a self-contained player spec and carries its own hex and
CRC bit helpers, like the two specs that already share hex_nibble_of;
crc_bits was unique until now. Recorded in the same commit as the specs,
per the gate's own instruction. build_tree 5 rides along from the merged
master specs.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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github-actions Bot commented Oct 7, 2026

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PR Dashboard

Generated at: 2026-10-07 22:24:46 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 49
PRs with All Checks Green 1
READY 1
FAILING 49
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=39fa3908f9fd != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag

gHashTag commented Oct 7, 2026

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Superseded by #7626: same specs, rebuilt as a clean three-commit chain on top of current master (root commit now carries the issue reference the L1 gate needs). The REST API cannot retarget a PR head branch, so the fixed history ships as a new PR; the old branch is left untouched.

@gHashTag gHashTag closed this Oct 7, 2026
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fpga: RGMII timing arithmetic and Ethernet FCS specs for the buses course

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