Skip to content

Port fpga/verilog/gft_signed_mac_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_signed_mac_jtag.t27 - #7333

Open
gHashTag wants to merge 3 commits into
masterfrom
queen-5180
Open

gHashTag wants to merge 3 commits into
masterfrom
queen-5180

Conversation

@gHashTag

@gHashTag gHashTag commented Oct 7, 2026

Copy link
Copy Markdown
Owner

Closes #5180

Written by a bee on queen-5180 and published by tools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.

1 file changed, 321 insertions(+)

🤖 Generated with Claude Code

Trinity Bee and others added 3 commits October 6, 2026 22:53
…t_signed_mac_jtag.t27

- Add module gft_signed_mac_jtag with JTAG test wrapper
- Implement MINORITY form signed multiplication behavior
- Add tests for ZERO, COMM, CANCEL, and IND properties
- Include JTAG scan chain simulation
- Add comprehensive test cases and invariants

Closes #5180
Ports fpga/verilog/gft_signed_mac_jtag.v (145 lines) to
specs/port/fpga/verilog/gft_signed_mac_jtag.t27:

- module gft_signed_mac_jtag, brace form, with JTAG_CHAIN_N = 3 and the
  16.16 fixed-point constants (ONE = 20480, TWO = 20992, NEG = 86016, Z = 0)
- STARTUPE2/BSCANE2/BUFG/GftSignedMac as external functions (undefined;)
- DUT arithmetic (magmul, magadd, magsub, smul, sadd, on_comb with RNE
  rounding) spliced verbatim from specs/ternary/gft_signed_mac.t27
  lines 16-134, re-indented +4 for the brace-form module -- the proven
  oracle, replacing the previous attempt's hand-invented mac model that
  could not equal 0 under RNE
- four clause properties mirroring the DUT's test block: zero (512),
  comm (both orderings == 20480), cancel (== 0), ind (== 20992)
- run_clauses settle latch (TestResults) and build_jtag_word (WORD v3,
  sibling smul port's proven form) exercised via benches
- 8 tests / 5 invariants: t27c test-report 8/8 pass, 5/5 proved,
  100% rate, no BLOCKED; t27c parse and typecheck clean; t27c gen-verilog
  emits module gft_signed_mac_jtag with clk/rst_n/en/ready

Closes #5180
A pull request must add exactly one docs/now entry and a bee has no way
to know that: its brief names a boundary file and acceptance criteria,
and docs/now/ is neither. The publisher adds it rather than failing the
gate.

Closes #5180

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
@gHashTag
gHashTag enabled auto-merge (squash) October 7, 2026 07:27
@gHashTag
gHashTag disabled auto-merge October 7, 2026 07:31
This was referenced Oct 7, 2026
This was referenced Oct 9, 2026

This branch has not been deployed

No deployments
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

Port fpga/verilog/gft_signed_mac_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_signed_mac_jtag.t27

2 participants