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tools: record t27core.t27 in the Verilog width ledger, exact arithmetic (Closes #8024) - #8025

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tools: record t27core.t27 in the Verilog width ledger, exact arithmetic (Closes #8024)#8025
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Closes #8024. Follows #8020 (P2 slice 5 of #5980). It turns Verilog widths (absurd-width ledger) green on master again.

#8020 moved the self-hosted core's tables from parallel i64 arrays into arrays of structs. t27c gen-verilog lowers the old arrays as memories ([0:262143]), but it packs an array of structs into one register:

array element bits
toks: [262144]Tok Tok { kind, pos, len: i64 }, 192 bits 50,331,648, so [50331647:0]
nodes: [262144]Node Node { 8 x i64 }, 512 bits 134,217,728, so [134217727:0]

These are not underflows: the widths match the emitter bit for bit. This is the same class as the two lines the ledger already holds, stdlib.t27 and ternary_memory.t27. Each of those has its arithmetic beside it, and the question of whether such a type should lower at all stays with #2566. The core is a compiler built for C, Zig and AArch64, not a hardware design.

Lines by file

file + - kind
tools/verilog_width_baseline.txt 16 0 ledger line, with its arithmetic as a comment

check_budget exit 0 and check_all exit 0. Both ran on the t27c lab with master's own_language.c and foreign-exceptions.txt.

Lab evidence

On the t27c lab, with t27c built from master and this branch, python3 tools/check_verilog_widths.py --require gives:

scanned 1697 spec(s) with target/release/t27c
      specs/base/ternary_memory.t27: 3801183
      specs/compiler/core/t27core.t27: 50331647,134217727
      specs/compiler/stdlib.t27: 4198431

OK: 3 known, 0 new.

🤖 Generated with Claude Code

@claude
tools: record t27core.t27 in the Verilog width ledger, exact arithmet…
eca7ab7 
…ic (Closes #8024)

#8020 moved the self-hosted core's tables into arrays of structs, which
gen-verilog packs into one register each: toks is 262144 * 192 = 50331648
bits and nodes 262144 * 512 = 134217728 bits. Not an underflow; the same
class as the two lines already recorded, with the arithmetic beside it.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-09 06:16:31 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 46
PRs with All Checks Green 4
READY 1
FAILING 46
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 46 + 0 + 0 = 47, and there are 50 open PRs. A PR is being counted twice or not at all.

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  • ⚠️ STALE -- sha256(compiler.rs)=3c0ade9e73e4 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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@gHashTag @claude
gen-verilog: hold a module-level array of structs as a memory; t27cor…
441e42f 
…e leaves the width ledger (Closes #8151) (#8154)

* gen-verilog: hold a module-level array of structs as a memory (Closes #8151)

A module-level `var` whose type is an array of structs was one packed
register. Since #8020 that made t27core's `nodes` 262144 * 512 =
134,217,728 bits (`toks` 50,331,648), the line #8025 added to
tools/verilog_width_baseline.txt. It is now an unpacked memory,
`reg [W-1:0] name[0:N-1]`, with W the struct's packed width: the form
W531 already gives an array of primitives, which is what these tables
were before #8020.

- The decision is specs/compiler/verilog_aos_memory.t27 (6 tests),
  lowered by `t27c gen-rust` to bootstrap/gen/rust/compiler/ and mounted
  by #[path]. A var initialized by a function call stays packed (W589,
  as W545 for primitives); so does an empty list.
- compiler.rs prints it: declaration, element and field access
  (`name[i]`, `name[i][off +: w]`) and literal initialization. 39
  hand-written lines added, 1 changed. FROZEN_HASH updated.
- t27core.t27 leaves the width ledger; the gate reports 2 known, 0 new.
  stdlib.t27 and ternary_memory.t27 stay: each is one struct of millions
  of bits, which a memory does not split (see #2566).
- Outputs changed for 9 of 2038 .t27 files, all the same conversion.
  Resealed gen_hash_verilog for the 4 sealed ones (mac, lotus,
  xc7a100t_minimal, similarity_search: 9 seal files); sealed the new spec.
  html, xml and terminal are left as master's ledgered debt.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* t27b ledger: list specs/compiler/verilog_aos_memory.t27 as pass (Closes #8151)

The t27b native ratchet reported the new spec UNLISTED: the reference and
t27b both pass it. Listed where a new spec is listed, in sorted order.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

---------

Co-authored-by: Claude <claude@anthropic.com>
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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Verilog widths gate red on master: t27core.t27's struct tables pack into 134217728-bit registers (exact, not an underflow)

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