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data(t27b): bless master run 13e212a5a (26 new specs, 8 up, cap 44 -> 67) - #6598
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PR DashboardGenerated at: 2026-10-05 21:34:01 UTC
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PR DashboardGenerated at: 2026-10-05 21:55:53 UTC
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Closes #6597
Refs #6063
This is tool-written data only:
docs/reports/t27b_expectations.jsonwas rewritten bypython3 scripts/tri_loop/t27b.py ratchet --run <lab run> --bless --accept-new.max_not_passgoes from 44 to 67. The +23 is exactly the 23 non-pass specs that are new to the ledger (bless accounting, t27b: bless accounts for a cap rise, doctor stops alarming on a fail the reference shares #6237). 0 named entries regressed and 0 entries were removed.specs/crons/trinity-site-live-gate.t27andspecs/tools/tri/{elab,emit,experience,fleet,fmt,fpga,gates}.t27. 0 entries move down.UNEXPECTED FAILURE 0, UNEXPECTED PASS 0, UNLISTED 0, STALE 0, OVER CAP 0, BAD REASON 0, MOVED 0, UNJUDGED 0, VACUITY MEASURED 0). Before the bless it was red: 8 UNEXPECTED PASS and 26 UNLISTED.Specs added (26), each with t27b's first blocker:
specs/api/c_abi.t27ExprBinary(value ignored) statementspecs/api/tri_api_context.t27ExprBinary(value ignored) statementspecs/api/tri_api_loop.t27ExprBinary(value ignored) statementspecs/api/tri_api_permissions.t27ExprBinary(value ignored) statementspecs/compiler/rust_tail_returns.t27ExprLiteral(value ignored) statementspecs/compiler/verilog_branch_context.t27ExprLiteral(value ignored) statementspecs/compiler/zig_field_syntax.t27ExprStructLit(zig keyword field)specs/compiler/zig_test_shadowing.t27StmtAssign(reference redeclares)specs/compiler/zig_value_ignored.t27ExprBinary(value ignored) statementspecs/fpga/bpsk.t27ExprCall(value ignored) statementspecs/fpga/linker.t27ExprStructLit(zig keyword field)specs/fpga/testbench/formal_tb.t27StmtAssign(module var in test)specs/fpga/testbench/vcd_trace_tb.t27StmtAssign(module var in test)specs/isa/ternary_encoding.t27ExprBinary(value ignored) statementspecs/isa/ternary_graph.t27ExprLiteral(value ignored) statementspecs/isa/tri27_bytecode.t27ExprBinary(value ignored) statementspecs/port/fpga/verilog/ternary_mac_synth.t27ExprArrayLiteral(reference empty typed)specs/port/trinity/fpga/openxc7-synth/definitive_diagnostic_inv.t27-specs/port/trinity/src/tri/string_dualities.t27ExprFieldAccessspecs/port/trios/crates/trios-scarab-types/rings/SR-03/src/lib.t27-specs/port/trios/crates/trios-scarab-types/rings/SR-04/src/lib.t27-specs/tools/catalog.t27ExprBinary(value ignored) statementspecs/tools/mcp_protocol.t27ExprBinary(value ignored) statementspecs/tri/crypto/hex.t27ExprStructLit(value ignored) statementspecs/vm/trinity_vm.t27ExprBinary(value ignored) statementspecs/vsa/trinity_compat.t27ExprBinary(value ignored) statement🤖 Generated with Claude Code