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fix(gen-verilog): array-param element index -> part-select (#1745) - #1748
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An [N]T array parameter lowers to a packed input [N*W-1:0] vector, but indexing it with a variable emitted a bit-select (xs[i]) instead of an element part-select, reading one bit (sum_arr([1,2,3,4]) returned 1, not 10). try_emit_primitive_array_access only recognised module/local packed arrays; add a param_types fallback via primitive_array_info so array params index by xs[i*W +: W]. Now sum_arr([1,2,3,4]) == 10. New regression test tests/verilog_array_param_index.rs; full compiler suite green (excl. pre-existing #1726); FROZEN_HASH re-sealed. Closes #1745 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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This was referenced Aug 5, 2026
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An
[N]Tarray parameter lowers to a packedinput [N*W-1:0]vector, but indexing it with a variable emitted a bit-select (xs[i]) instead of an element part-select — so it read one bit instead of the W-bit element. Confirmed by simulation:sum_arr([1,2,3,4])returned 1, not 10.Closes #1745
Fix
try_emit_primitive_array_accessrecognised only module- and local-scope packed arrays; array-typed parameters fell through to the naive bit-select. Added aparam_typesfallback (viaprimitive_array_info) so an array param is indexed byxs[i*W +: W], matching the packing used for its declaration.Verification
xs[i]now lowers toxs[((i) * 64) +: 64];sum_arr([1,2,3,4]) == 10under iverilog+vvp.tests/verilog_array_param_index.rs(asserts part-select + correct sum; skips without iverilog).bitnet_topreds (test: bitnet_top asserts stale contract (busy + mem tie-off) vs current gen-bitnet-engine-top #1726).Unblocks fully-parameterized loops over packed-array inputs — e.g. an N-chunk BitNet neuron over a
[N]u64weight/activation array (the neuron in #1746 had to use separate scalar params as a workaround).🤖 Generated with Claude Code