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t27b: integer types of odd width 1..31 (type u1, i2, u4, u21) (Closes #7368) - #7398

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@gHashTag gHashTag commented Oct 7, 2026 •

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Refs #6063. Closes #7368.

What

t27b refused every integer type whose width is not 8, 16, 32 or 64 (type u1, type i2, type u4, type u21). Zig has an integer of every width and t27c prints the spelling unchanged, so the reference already runs these specs. specs/port/trinity/fpga/openxc7-synth/led_off_test.t27 was blocked on type u1 alone.

t27b now has an integer type of every width 1..31 other than 8 and 16:

  • A value is held like a u8: in a W register, zero-extended (unsigned) or sign-extended (signed).
  • After + - * the result is checked against the type's own range (ubfx/sbfx, then compare). A product of more than 16 bits is formed with umull/smull, so one past 2^32 still traps.
  • ~ on an unsigned odd width flips only its own bits. << drops the bits that leave the type, as Zig does; a constant amount is checked against the width, not masked with bits - 1 (that mask would turn x << 5 on a u21 into x << 4, in eval and codegen alike -- fixed in both).
  • Checked as casts and enum tag types take odd widths too.

Still refused, by name:

  • A wrap-mode shift by a runtime amount on an odd width (ExprBinary(<< >>)): bits - 1 is not a mask there.
  • Widths 33..63 (type u48) and 128 and above (type u128 .. type u1024, type i128): they need register pairs or a multi-limb lowering, later slices of lane 3.

Dogfood spec first

specs/tri/t27b/conformance/odd_width_int.t27, 9 tests. Results on the Railway t27c lab:

  • Reference (t27c test-report, master t27c): 9 pass, 0 vacuous, 57 runtime asserts. It was run before any Rust was touched.
  • t27b: 9 pass in trap mode and in wrap mode, 57 asserts.
  • 14 mutants (wrong values, and inputs that overflow u4, i2, i21 and u31): each fails the same single test in t27b and in the reference.
  • cargo test --release -p t27b --target aarch64-unknown-linux-gnu under qemu-user on the lab: 14 suites, 125 passed, 0 failed. tests/differential.rs now runs every binary operator, unary op, widening and cast at the edge values of twelve odd widths (u1, i1, i2, u4, i5, u7, u17, i17, u21, i21, u31, i31), plus every constant shift amount, JIT against eval.

Numbers (t27b corpus specs, Railway t27c lab, aarch64 under qemu-user, both binaries on the branch tree)

master cd6708d branch 19c45d4
files 1526 1526
pass 819 821
pass_vacuous 143 143
fail 18 18
blocked 541 539
mismatch / jit_interp_mismatch 0 / 0 0 / 0

Every changed verdict:

  • specs/port/trinity/fpga/openxc7-synth/led_off_test.t27: blocked (type u1) -> pass, 1 test, 1 assert. The reference passes it (t27b lab run e45ba56).
  • specs/tri/t27b/conformance/odd_width_int.t27: new, pass, 57 asserts.
  • Four specs move to their next blocker, all in other lanes: specs/igla/race/rtl.t27 (type u1 -> ExprBinary(+) on a string), specs/numeric/gf4.t27 (type u4 -> ExprIdentifier(E::V)), specs/port/trinity/src/brain/weber_tuning.t27 (type i2 -> ExprCall(@abs)), specs/tri/utils/utf8.t27 (type u21 -> type std.mem.Allocator). None of them is in the ledger.

The master numbers match the t27b lab's own run on e45ba56 (819 pass, mismatch 0): https://t27b-lab-production.up.railway.app/runs/e45ba566d08f5bb36de304ca7061a202d37d58de.json

Ledger docs/reports/t27b_expectations.json: led_off_test.t27 and the new spec move to pass; counts recomputed after the merge with master 05e633d: pass 535, not_pass 24, max_not_pass 24.

Foreign-code approval

The owner's standing rule: "add the label yourself and do the foreign part" (translated). The label owner-approved-foreign is on this PR. The edit touches cli/t27b/src/{ir,codegen,eval,lower}.rs and cli/t27b/tests/differential.rs, each listed in tools/policy/foreign-exceptions.txt (new block for #7368 at the top). The spec that will replace this Rust is the t27b port, epic #6198. The AGENTS.md debt line is updated: 15453 plus 7719 lines (+111 and +42).

🤖 Generated with Claude Code

gHashTag and others added 2 commits October 7, 2026 15:36
…7368)

A value of an odd-width integer type is held like a u8: in a W register,
zero- or sign-extended, and checked against its own range after + - *
(ubfx/sbfx and compare). A product of more than 16 bits is formed with
umull/smull, so one past 2^32 still traps. ~ on an unsigned odd width
flips only its own bits, and << drops the bits that leave the type.
A runtime wrap-mode shift amount on an odd width is refused by name.

Conformance spec first: specs/tri/t27b/conformance/odd_width_int.t27.

Refs #6063.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…loses #7368)

Refs #6063

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@gHashTag gHashTag added the owner-approved-foreign Owner-approved exception to the only-t27 rule: hand-written foreign code allowed in this PR label Oct 7, 2026
@gHashTag
gHashTag enabled auto-merge (squash) October 7, 2026 08:52
Closes #7368)

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-07 09:24:15 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 39
PRs with All Checks Green 11
READY 1
FAILING 39
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 39 + 0 + 0 = 40, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=1aa228450491 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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t27b: integer types of odd width 1..31 (type u1, i2, u4, u21)

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