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crm-story-reel v28: a retry renders only the empty clip slots - #7000

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gHashTag wants to merge 1 commit into

feat/crm-story-reel-v27-gallery-previewfrom

feat/crm-story-reel-v28-retry-reuses-clips

gHashTag commented Oct 6, 2026

Owner

Stacks on #6980 (v27); base is its branch, retarget to master after #6980 merges.

Closes #6999. Refs gHashTag/999-multibots-telegraf#3804.

slots_to_render(total, done) = total - done (0 when done >= total)
retry_price charges only those slots
slot_renders(done) is false for a done slot
VERSION 28 + VERSION test, seal saved
t27c test-report: 66 pass, 0 FAIL; new test runs 11 asserts
Negative control: slots_to_render returning slots_total -> the new test FAILs; restored

Spec only; host code in 999 not touched (needs owner-approved-foreign).

🤖 Generated with Claude Code


          feat(crm-story-reel): v28 a retry renders only the empty clip slots

77537d5

A failed job threw away clips already made (999#3804, jobs 10 and 11).
slots_to_render(total, done) = total - done, retry_price counts only
those, slot_renders(done) is false for a done slot. 66/66; mutant
(return slots_total) turns the new test red.

Refs #6999

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

This was referenced Oct 6, 2026

spec(crm-story-reel): v27 gallery preview draws the render's end-card defaults (Refs #6973) #6980

Open

Port bootstrap/src/compiler.rs lines 30624-30746 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/VcdVarKind_vcd #6982

Open

gen-verilog and gen-verilog-hir: hello_world.t27 output is refused by iverilog, verilator and yosys #6987

Open

feat(t27b): --check interpreter fuel per file, policy in check_budget.t27 (Closes #6664) #6695

Merged

Port gHashTag/trinity:fpga/openxc7-synth/blink_fixed.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blin #6985

Open

This was referenced Oct 6, 2026

crm-story-reel v29: brand kit -- saved client palette on every preview and the rendered end card #7008

Open

crm-story-reel v29: brand kit on every preview and the rendered end card #7009

Open

This was referenced Oct 6, 2026

fix(numeric): settle gf16.t27 against FORMAT-SPEC-001 -- no subnormals, ties toward zero, NaN 0xFE01, exponent mask (#6940) #6969

Merged

Port bootstrap/src/compiler.rs lines 29796-29869 (Rust, 10 functions) to specs/port/bootstrap/src/compiler/HirIpCatalog_ #6986

Open

Port bootstrap/src/enrichment/mod.rs (Rust, 2 functions) to specs/port/bootstrap/src/enrichment/mod.t27 #6983

Open

fix(codegen): gen-rust enum order and gen-zig float-call cast (#6941) #6994

Open

Port bootstrap/src/compiler.rs lines 28704-28852 (Rust, 7 functions) to specs/port/bootstrap/src/compiler/HirClockDomain #6984

Open

t27b: an untyped var takes the reference's u32/u64 width; an untyped undefined const is accepted (Closes #6967) #6998

Merged

Port scripts/gen_w633.py (Python, 3 functions) to specs/port/scripts/gen_w633.t27 (Closes #6711) #6997

Merged

feat(fpga): PoC slots a/b on silicon -- one JTAG boundary, two implementations (Closes #6829) #6832

Merged

fix(spec-guards): ring-096 and specs/numeric/formats.t27 agree on f32, as the gf16 SSOT says #6894

Closed

spec(queen): actors control lane, call, backoff, hung turn, dead letters (Closes #6972 #6974 #6975 #6976 #6990 #6991 #6992) #7001

Merged

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/queen-lease.ts (TypeScript, 6 functions) to spec #7011

Open

Port fpga/vivado/gf16_top.v (Verilog, 1 module) to specs/port/fpga/vivado/gf16_top.t27 #7012

Open

Port bootstrap/src/compiler.rs lines 1-264 (Rust, 3 functions) to specs/port/bootstrap/src/compiler/Node_default.t27 #7017

Open

t27b: untyped var from an integer literal, unread undefined const (StmtLocal) (Closes #6995) #7010

Closed

Port gHashTag/trinity:src/api/depin_rest.zig (Zig, 2 functions) to specs/port/trinity/src/api/depin_rest.t27 #7014

Open

Port gHashTag/trinity:src/tri/gen_sigmoid.zig (Zig, 2 functions) to specs/port/trinity/src/tri/gen_sigmoid.t27 #7019

Open

Port bootstrap/src/compiler.rs lines 30884-30976 (Rust, 8 functions) to specs/port/bootstrap/src/compiler/LinkSection_te #7013

Open

Port bootstrap/src/compiler.rs lines 28398-28603 (Rust, 5 functions) to specs/port/bootstrap/src/compiler/HwType_hw_widt #7015

Open

Port bootstrap/src/check_calls.rs (Rust, 7 functions) to specs/port/bootstrap/src/check_calls.t27 #7016

Open

Port gHashTag/trios:crates/trios-ternary/rings/TR-01/src/lib.rs (Rust, 2 functions) to specs/port/trios/crates/trios-ter #7018

Open

Port scripts/lee_monte_carlo_baseline.py (Python, 2 functions) to specs/port/scripts/lee_monte_carlo_baseline.t27 #7020

Open

Port gHashTag/trinity:src/tri/sacred_constants.zig (Zig, 1 function) to specs/port/trinity/src/tri/sacred_constants.t27 #7031

Open

This was referenced Oct 6, 2026

Port gHashTag/trios:crates/trios-cli/src/cmd/run.rs (Rust, 5 functions) to specs/port/trios/crates/trios-cli/src/cmd/run #7035

Open

Port tools/backend_parity_table.py (Python, 4 functions) to specs/port/tools/backend_parity_table.t27 #7039

Open

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/services/terminal/terminal-session.ts (TypeScript, 3 func #7038

Open

Port fpga/vivado/blinky.v (Verilog, 1 module) to specs/port/fpga/vivado/blinky.t27 #7037

Open

silicon: every hardware run writes a receipt artifact (R2-1/R2-2) (Closes #7041) #7044

Merged

Port gHashTag/trinity:fpga/openxc7-synth/blink_test_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/b #7040

Open

t27b: fold compile-time float arithmetic in binary128, as Zig does (Closes #7021) #7042

Closed

feat(tri): tri mutate spec -- guard, operator and arithmetic mutants of a .t27 spec (Closes #6993 #7022) #7043

Merged

Port scripts/ci/rings_matrix.py (Python, 2 functions) to specs/port/scripts/ci/rings_matrix.t27 #7046

Open

Implement the 9 empty function bodies in specs/ml/transformer/mha_block.t27 #7048

Open

Port scripts/gen_w309.py (Python, 3 functions) to specs/port/scripts/gen_w309.t27 #7047

Open

Port gHashTag/trinity:src/tri/gen_record_store.zig (Zig, 4 functions) to specs/port/trinity/src/tri/gen_record_store.t27 #7049

Open

Port gHashTag/trinity:fpga/openxc7-regress/regress-fabric-bufg/fabric_bufg.v (Verilog, 1 module) to specs/port/trinity/f #7054

Open

Port gHashTag/trios:crates/trios-git/src/status.rs (Rust, 1 function) to specs/port/trios/crates/trios-git/src/status.t2 #7051

Open

Port gHashTag/trios:crates/trios-scarab-types/rings/SR-02/src/lib.rs (Rust, 6 functions) to specs/port/trios/crates/trio #7056

Open

Port scripts/gen_w388.py (Python, 2 functions) to specs/port/scripts/gen_w388.t27 #7053

Open

Port gHashTag/trinity:src/storm/experience_engine.zig (Zig, 3 functions) to specs/port/trinity/src/storm/experience_engi #7052

Open

Port gHashTag/trinity:src/tri/gen_radix_tree.zig (Zig, 6 functions) to specs/port/trinity/src/tri/gen_radix_tree.t27 #7055

Open

t27b: a comptime_float is a binary128 value, folded like Zig (Closes #7007) #7045

Merged

Port gHashTag/trinity:fpga/openxc7-synth/blink_fast.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/blink #7064

Open

verified: run_record -- when a set of receipts is one verified run (R2-4 spec half) #7061

Merged

spec(queen): actors jitter, significant children, call cycle, max children; control.t27 effects journal (Closes #7002 #7003 #7004 #7005 #7006) #7060

Merged

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/tools/clade-improve-tool.ts (TypeScript, 1 function) to specs #7063

Open

Implement the 4 empty function bodies in specs/tri/graph/graph_bfs.t27 #7065

Open

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/lib/clients/oauth/token-store.ts (TypeScript, 5 functions) to #7068

Open

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/routes/queen-public-earnings.ts (TypeScript, 1 function) #7067

Open

Port gHashTag/BrowserOS:trios/agent-server/apps/server/src/api/routes/queen-public-credits.ts (TypeScript, 1 function) t #7066

Open

Port gHashTag/trinity:src/tri/gen_hash_table.zig (Zig, 4 functions) to specs/port/trinity/src/tri/gen_hash_table.t27 #7069

Open

Port gHashTag/trios:crates/trios-cli/src/cmd/sweep.rs (Rust, 4 functions) to specs/port/trios/crates/trios-cli/src/cmd/s #7070

Open

Port gHashTag/trios:crates/trios-train-cpu/src/bin/train_state.rs (Rust, 4 functions) to specs/port/trios/crates/trios-t #7071

Open

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