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fix(fpga): build_verify counts measured from the tree; reseal (Closes #6659) - #6660
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… stale baseline lines Closes #6659 #1399 set TOTAL_FPGA_MODULES = 33 / TOTAL_BOARD_CONFIGS = 3 / TOTAL_SPECS = 66 while test_module_count still asserted 31, so the spec could not be sealed. Measured on master 099ac22: 36 modules, 30 testbenches, 2 boards, 68 total, all 68 generate Verilog on the Railway lab. test-report 11/11; a mutated count (35) fails two tests. Resealed on the lab; BuildVerify and verification_BuildVerify leave tools/seal_baseline.txt. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Closes #6659
What
specs/fpga/verification/build_verify.t27:TOTAL_FPGA_MODULES33 -> 36,TOTAL_BOARD_CONFIGS3 -> 2,TOTAL_SPECSandVERILOG_FILES66 -> 68, tests assert the same values. Counts measured on master 099ac22 (specs/fpga/*.t2736,testbench/30,boards/2);t27c gen-verilogsucceeds on all 68 on the Railway lab.BuildVerify.json,verification_BuildVerify.json.tools/seal_baseline.txt: the twostalelines removed (stale 30 -> 28). Nothing added.docs/now/2026-10-06-build-verify-counts.md.Evidence (Railway t27c lab)
t27c test-report: 11/11 pass (was 10/11,test_module_countfailing).TOTAL_FPGA_MODULES = 35failstest_module_countandtest_total_specs.check_seal_coverage.py: OK, 1456 seals, 1314 hold, 142 known-broken.check_seal_currency.py: BuildVerify no longer listed.🤖 Generated with Claude Code