Merge branch 'master' into claude/gen-zig-spliced-type

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GitGuardian

GitGuardian Security Checks

Issue Gate on: pull_request_target 2

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Spec Parse Ratchet on: pull_request 2

parse-ratchet

Wasm Explorer on: pull_request 7

build-and-test

Documented Commands on: pull_request 2

Documented t27c subcommands exist

PR Dashboard on: pull_request 1

pr-dashboard

Conflict Markers on: pull_request 2

Conflict markers (no unresolved merges)

Verilog Widths on: pull_request 2

Verilog widths (absurd-width ledger)

Seal Staleness Warning on: pull_request 2

Warn if NMSE seal is stale vs compiler.rs

Bootstrap Test Ratchet on: pull_request 5

test-ratchet

Emit Bit-Exact Gate (CI-02) on: pull_request 2

emit-bitexact

Harness scratch directories on: pull_request 2

No test binary shares one scratch directory

Untrusted Input Gate on: pull_request 1

untrusted-input

Duplicate Body Ratchet on: pull_request 1

duplicate-bodies

Gate Topology on: pull_request 1

gate-topology

Corpus Ratchet on: pull_request 2

Corpus ratchet (expected-failure ledger)

PHI Loop CI on: pull_request 1

phi-loop-check

Withdrawn Number Gate on: pull_request 2

withdrawn-live

L1 TRACEABILITY Check on: pull_request 3

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L1 Traceability Summary

secret-scan on: pull_request 1

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Orphaned modules on: pull_request 2

Every source file is reachable from its crate root

Damage Negatives on: pull_request 2

Damage negatives (false-positive fixtures)

cli-tri on: pull_request 3

cli-tri

Own Language on: pull_request 1

own-language

Fix Carries Source on: pull_request 1

fix-carries-source

FPGA E2E Build on: pull_request 16

fpga-smoke

fpga-lint (read_verilog + hierarchy)

fpga-synthesis

fpga-synthesis-arty

fpga-formal

fpga-conformance

fpga-bitstream

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Spec Guards on: pull_request 3

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Seal Coverage on: pull_request 2

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Schema Validation on: pull_request 2

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