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feat(xilinx7): 7-series configuration packets as a .t27 spec (Closes #5608) - #5609

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feat(xilinx7): 7-series configuration packets as a .t27 spec (Closes #5608)#5609
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Closes #5608
Refs #5606, #5607

What

  • specs/xilinx7/packets.t27: the Xilinx 7-series configuration packet stream as one spec.
    • Type-1 / Type-2 header decode and opcodes.
    • Series-7 register and command numbers.
    • FAR fields and the frame size (101 words).
    • The running CRC: CRC32C 0x82F63B78, fed 32 data bits then the 5-bit register address. A CRC write compares and resets; CMD RCRC resets.
    • The COR0 field table.
    • resealed, which rewrites a CRC word only if the original one passed.
    • Each section cites prjxray c9f02d857 by file and line.
  • specs/xilinx7/bitwalk.rs: a driver built from t27c gen-rust. It does file I/O and the loop; every decision is a spec function. Build steps are in both file headers. The generated packets.rs and the binary are gitignored.
  • docs/now/2026-10-02-xilinx7-packets-spec-reproduces-vivado-crc.md.

Measured

  • t27c test-report specs/xilinx7/packets.t27: 10 pass, 0 fail. The CRC oracle is a value Vivado wrote (0xE3AD7EA5), not one the spec computed.
  • Over 6 Vivado bitstreams (2 local designs plus the 4 prjxray-db/artix7/harness bitstreams), all 12 CRC checks reproduce; bad 0.
  • Two openXC7 (xc7frames2bit) bitstreams contain no CRC write at all.
  • patch_cor0's approach, rewriting only the COR0 word, leaves a Vivado bitstream with 1 of 2 CRC checks wrong (bitwalk --cor0 5 --no-reseal). With resealed, 2 words change and bad is 0.
  • The COR0 fields decoded from the table equal what scripts/dump_bit_config.py prints for the same files.

Limitations

Later commits on this branch

Each commit has its own docs/now/ entry with the measurements and the limits.

  • Frame ECC (frames.t27). It recomputes the ECC of 32,520 of 32,520 Vivado frames.
  • FAR walk (far.t27, xc7a35t / 100T / 200T, part picked by IDCODE).
    • Each Vivado FDRI write equals the walked frame list.
    • 82/82 constrained pins.
    • 4224/4224 set bits named by a tile's segbits.
  • Writer (bitwalk --write). Frames to .bit, byte-identical to xc7frames2bit on 16/16.
  • FASM to frames (bitwalk --fasm, segbit positions in frames.t27).
    • Byte-identical to fasm2frames on 20/20: 13 real designs, 5 synthetic, and 2 refuse files
      refused for the same reason.
    • 4 of the 4 runnable reference-parity cases of testdata: the reference chain's frames as gold standards, with a check lromor/fpga-assembler#49.
    • --strict refuses bits outside their tile. fasm2frames writes an absent *_SING site's
      bits into word 100 of the frame, which another tile owns.
    • Measured here: about 0.1 s per real xc7a100t design, against 1.2-1.6 s for fasm2frames.

Still not shown: no board has been configured with any output of this branch. No xc7a200t FASM
is in the corpus, and there is no Vivado reference for 100T or 200T.

🤖 Generated with Claude Code

@gHashTag @claude
feat(xilinx7): 7-series configuration packets as a .t27 spec (Closes #…
1d85e83 
…5608)

specs/xilinx7/packets.t27 holds the packet grammar, Series-7 register and
command numbers, FAR layout, the running CRC and the COR0 field table, each
cited from prjxray c9f02d857. 10/10 tests; the CRC oracle is a value Vivado
wrote. bitwalk.rs, built from t27c gen-rust, reproduces all 12 CRC checks in
6 Vivado bitstreams, and `resealed` keeps the CRC valid after a COR0 rewrite
where rewriting COR0 alone leaves 1 of 2 checks wrong.

Closes #5608
Refs #5606
Refs #5607

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-02 15:48:01 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 46
PRs with All Checks Green 4
READY 3
FAILING 46
PENDING 0
NO CHECKS YET 0

These columns do not partition: 3 + 46 + 0 + 0 = 49, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag gHashTag mentioned this pull request Oct 2, 2026
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@gHashTag @claude
feat(xilinx7): table-driven CRC32C in packets.t27, derived and tested…
7dcc711 
… (Refs #5608)

The bitwise CRC (37 bit steps per written word) was ~90% of bitwalk's time.
Add CRC32C_TABLE, crc_byte and crc_word (4 lookups + 5 bit steps) and route
crc_after through it. crc_step stays as the bitwise definition.

The table is not trusted: crc_table_is_derived recomputes all 256 entries
from crc_bit, and crc_word_equals_crc_step compares both forms over 4096
xorshift32 pairs. Mutating one table bit or dropping one byte step fails
them. 12/12 tests; bitwalk still reproduces all 12 Vivado CRC checks.

The docs/now entry withdraws the earlier 0.3-0.9 s figure (taken at load
~45) and records the measured before/after with its load.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-02 16:20:26 UTC

Summary

Status Count
Total Open PRs 46
PRs with Failing Checks 41
PRs with All Checks Green 5
READY 1
FAILING 41
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 41 + 0 + 0 = 42, and there are 46 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag and others added 2 commits October 2, 2026 23:34
@gHashTag @claude
feat(xilinx7): frame ECC as a .t27 spec, checked on 32,520 Vivado fra…
7942f72 
…mes (Refs #5608)

specs/xilinx7/frames.t27 states the 13-bit ECC in word 50 of every 7-series
frame, citing prjxray ecc.cc. Three frames copied from a Vivado bitstream are
the in-spec oracle (7/7 tests). bitwalk recomputes the ECC of every FDRI frame
through the generated module: 6 Vivado bitstreams, 32,520 frames, bad 0.
Four deliberate defects each fail the tests and the sweep.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@gHashTag @claude
test(xilinx7): frames.t27 agrees with fpga-assembler's ECC vectors (R…
4fa7447 
…efs #5608)

The six vectors lromor/fpga-assembler pins in arch-xc7-frame_test.cc for the
same function, added as one test. 8/8. They are computed from the rule, not a
device; the Vivado frames remain the oracle.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-02 16:43:16 UTC

Summary

Status Count
Total Open PRs 43
PRs with Failing Checks 40
PRs with All Checks Green 3
READY 1
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 40 + 0 + 0 = 41, and there are 43 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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Generated at: 2026-10-02 16:46:03 UTC

Summary

Status Count
Total Open PRs 43
PRs with Failing Checks 40
PRs with All Checks Green 3
READY 1
FAILING 40
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 40 + 0 + 0 = 41, and there are 43 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

This was referenced Oct 2, 2026
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@gHashTag @claude
feat(xilinx7): FAR walk as a .t27 spec, checked against Vivado FDRI w…
e0824a2 
…rites, pin tiles and segbits (Refs #5608)

far.t27 states the 7-series frame address layout and the order a
multi-frame FDRI write visits addresses, with two pad frames after every
(block, half, row) group. The xc7a35t part table is generated from
prjxray-db part.json between markers and drift-checked.

Checked against six Vivado xc7a35t bitstreams: every FDRI write is the
walked 5420 frames, all 72 pad frames are empty, 82/82 constrained pins
land in IOB frames with data, and 4224/4224 set bits are named by some
tile's segbits at the walked frame (bitwalk --pins, --bits). Five
mutations fail both the spec tests and the sweep.

The FAR layout moves here from packets.t27 (no cross-module use in t27c
yet), so the rule keeps one home.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-02 17:09:24 UTC

Summary

Status Count
Total Open PRs 43
PRs with Failing Checks 41
PRs with All Checks Green 2
READY 1
FAILING 41
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 41 + 0 + 0 = 42, and there are 43 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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@gHashTag @claude
feat(xilinx7): FAR walk for xc7a100t and xc7a200t, part picked by IDCODE
d28e54d 
far.t27's part table now covers xc7a35t, xc7a100t and xc7a200t, rendered
from prjxray-db part.json/part.yaml by `tri x7-part` and drift-checked on
every audit. Every walk function takes the part; bitwalk picks it from the
IDCODE the stream writes.

- xc7a35t: unchanged against Vivado (5420 frames x6, pins 82/82,
  segbits 4224/4224, 11/11 mutations caught).
- xc7a100t: 9464 frames, equal to hb.bit (xc7frames2bit) and to an
  in-house openXC7 build.
- xc7a200t: 24080 frames, equal to an xc7frames2bit 200T bitstream.

The larger parts have no Vivado reference here; the header says so. New
test every_part_index_meets_its_walk ties fdri_index to part_fdri_frames
for all 24 groups; ignoring the part offset fails it.

Refs #5608

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Reviewer bee: evidence and verdict for head e0824a2d. Not merging yet. Four items below need to change.

What I checked myself. I used a temp clone and a t27c built from master 5b2f8e478 (cargo build --release -p t27c).

  • t27c test-report: packets 11/11, frames 8/8, far 6/6.
  • Mutation controls. Each one turns tests red:
    • Vivado CRC oracle 0xE3AD7EA5 changed to …A4: crc_matches_vivado_tail FAILS.
    • part_fdri_frames() == 5418: walk_covers_vivado_fdri_write FAILS.
    • The parity step in ecc_after dropped: 3 tests FAIL, including ecc_matches_vivado_frame_1605.
  • None of the tests is an empty invariant.
  • gen-rust for all three specs, then rustc -O bitwalk.rs, builds.
  • bitwalk over the 6 Vivado bitstreams (vivado/vendor/{A_direct,B_idelay}_top.bit and prjxray-db harness arty-a7/{pmod,swbut,uart} and basys3/swbut):
    • CRC: 12 checks, bad 0.
    • ECC: 6 × 5420 = 32,520 frames, bad 0. Frames with data: 77+86+112+138+95+244 = 752.
    • FAR walk: 5420, off by 0. Pad frames with data: 0.
  • --cor0 5 --no-reseal: CRC bad 1 of 2. --cor0 5 with reseal: 2 words patched, bad 0, COR0 0x020A3FE5.

These claims reproduce. What is still missing:

  1. No seals. The three new specs ship without .trinity/seals/*.json. Every recent spec-adding PR shipped its seal: spec(automation): kanban-card-chat -- a card opens its agent conversation #5389, feat(automation): ball-grants -- the mail cards, to others only by the owner's grant (Closes #5387) #5411, automation/meta-connect: Threads, Instagram and a Facebook Page through Meta's API #5523, automation/social-api: LinkedIn and X as API connectors (Closes #5582) #5584, spec(automation): agent-conversations — several chats per agent #4840. I ran a dry t27c seal (no --save) with the master t27c, and all four backends accept all three specs. So this is t27c seal --save specs/xilinx7/{packets,frames,far}.t27 and a commit.
  2. tri x7-part is not in this repo. far.t27 says the part table is "generated by tri x7-part, do not edit", and the NOW entry says it is "checked for drift on every audit". git grep x7-part on this branch finds only those two mentions. The generator lives in a private skill (xilinx7-bitstream-loop/scripts/x7.py). Do one of these:
    • commit the generator and its drift check here, or
    • reword the marker to the reproducible source (prjxray-db artix7/xc7a35tcsg324-1/part.json, and how the table was derived) and drop the drift-check claim.
  3. Stale test counts. docs/now/2026-10-02-xilinx7-packets-spec-reproduces-vivado-crc.md says packets is 12/12, and the PR body says 10/10. On this head it is 11/11, because the FAR round-trip test moved to far.t27. Correct the NOW entry and the body.
  4. Corpus re-take. This adds 3 specs. untrusted-input is already red on master: master walks 1151 and the doc never states 1151 (see docs(igla): re-take the corpus figures on master, 1150 specs (Refs #5497) #5610, which is itself stale). By this repo's convention, the spec-adding PR re-takes the figures after it rebases on the re-take.

The other red gates (coverage, spec-guards seal drift on tri/* and ml/*, emit-bitexact gft_sadd Zig) are red with the same causes on master 5b2f8e478 and on #5613/#5605, and are not caused by this PR. Closes #5608 is present, and the NOW headers pass check-now-freshness.

@github-actions github-actions Bot mentioned this pull request Oct 2, 2026
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@gHashTag @claude
feat(xilinx7): write .bit from frames via the specs, byte-identical t…
0f5a4ef 
…o xc7frames2bit (Refs #5608)

packets.t27 now holds the 42-step packet sequence xc7frames2bit writes
around the frame data, cited to prjxray c9f02d857 and tested against an
xc7frames2bit bitstream (57 words before FDRI, 524 after, register words).

bitwalk --write places .frames at far.t27's fdri_index, seals ECC with
frames.t27 and emits the SEQ steps plus the .bit header. bitwalk --frames
dumps a .bit back to .frames.

Measured: byte-identical to xc7frames2bit on 8/8 xc7a100t pairs and on
frames dumped from 6 Vivado xc7a35t and 2 xc7a200t bitstreams, whose FDRI
payload also equals the original's. xc7a100t frames handed over as xc7a200t
are refused (192 foreign addresses, exit 1); xc7frames2bit writes them with
exit 0 and 192 extra frames.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-02 17:47:25 UTC

Summary

Status Count
Total Open PRs 40
PRs with Failing Checks 38
PRs with All Checks Green 2
READY 1
FAILING 38
PENDING 0
NO CHECKS YET 0

These columns do not partition: 1 + 38 + 0 + 0 = 39, and there are 40 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=c4c8259e027d != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@github-actions github-actions Bot mentioned this pull request Oct 2, 2026
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@dmitrii-f-t27 dmitrii-f-t27 closed this pull request by merging all changes into master in 82e5aa1 Oct 4, 2026
dmitrii-f-t27 added a commit that referenced this pull request Oct 4, 2026
@dmitrii-f-t27
fix(xilinx7): integrate sourced packet rules and restore corpus ratchet
616d847 
Retain original PR5609's nine upstream commits, three specifications,
Rust driver, six receipts and test oracles. Resolve the add/add packet
conflict to the original sourced grammar and CRC/ECC rules, preserving
current master fixes. Add one receipt with this review's actual proof.

35existing Zig tests,37,048original-C++/generated-Rust observations,
three meaningful negative controls and full-file COR0/CRC cases pass.
Fast corpus95/95CLEAN without ledger edits. Full hardware/Vivado/FASM
verification and all-green repository health are not claimed.

Closes #5870
Refs #5608, #5609
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xilinx7: 7-series configuration packets as a .t27 spec

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