Port gHashTag/trinity:fpga/openxc7-synth/d6_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/d6_test. - #5485
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Create specs/port/trinity/fpga/openxc7-synth/d6_test.t27 as a module trinity_top that replicates the original Verilog behavior. The original module has a simple clock input and LED output, with the LED always driven to 0 (active-low = ON). The port includes: - Module interface with clk input and led output - led_state() function that always returns false (ON for active-low) - compute_output() function that creates the module interface - is_led_on() helper for LED state interpretation - Tests verifying LED behavior and consistency - Invariants for LED consistency and output matching - Benchmarks for latency measurement Closes #5480
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5480 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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October 1, 2026 23:32
This was referenced Oct 1, 2026
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Closes #5480
Written by a bee on
queen-5480and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code