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… OSCFSEL theorem library Closes #1343 - Add --pvt-context to tri fpga measure-cclk --validate and measured-to-lean. - Harden VCD parser: multi-line $var, scalar/bus mixed dumps, duplicate transitions, $dumpoff/$dumpon regions. - Add OSCFSEL 0..7 nominal and worst-case PVT measured-CCLK theorems. - Update fpga/HARDWARE_SSOT.md and docs/NOW.md. - Reseal generated-code hashes. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-07-04 15:46:47 UTC
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Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-07-04 15:48:55 UTC
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This was referenced Jul 4, 2026
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Superseded by #1351 (clean rebase onto current master). Closing. |
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Closes #1343\n\nWave Loop 15 delivers Variant C (bench still blocked): PVT-aware validation for
tri fpga measure-cclkandmeasured-to-lean, VCD parser hardening, and a complete OSCFSEL 0..7 measured-CCLK theorem library.\n\n-cargo test -p tri fpga::tests: 32/32 PASS\n-lake build Trinity.TernaryFPGABoot: PASS\n-./scripts/tri test: seal-verify and code-generation phases PASS; 16 pre-existing gen-verilog-yosys-smoke failures in scratch specs.\n\n🤖 Generated with Claude Code