why the code of VendingMachineSwitch.scala in the tutorial generate if-else statement instead of case statement #151

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1. schoeberl commented on Sep 17, 2019

   

   schoeberl

   on Sep 17, 2019

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   You need to include chisel3.util._ and use a switch. See an example here: https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/SimpleFsm.scala
2. qgzln commented on Sep 20, 2019

   

   qgzln

   on Sep 20, 2019

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   Thank you for your reply.It is my fault.I didn't make it clear, I mean there is no case in the generated Verilog statement, I usually use the case when writing the state machine with Verilog. So, chisel3 still can not generate Verilog code with case？