regmap

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logvik-org / bust

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bust generates the register file of a register map from a JSON for FPGA or ASIC modules.

asic fpga vhdl python3 avalon registers wishbone axi register-file ipbus regmap

Updated Oct 23, 2026
Python

charkster / i2c_and_spi_shared_regmap

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A shared regmap with 2 bus interfaces (I2C and SPI 3wire). Three different clock domains all handled cleanly with an extremely simple bus arbitration.

i2c-bus arbitration spi-bus regmap

Updated May 2, 2025
SystemVerilog

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