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2025 Beijing University IC Design Competition - FPGA digital design. AXI-Stream network protocol parser (IPv4/ICMP) + 8-bit single-bus processor. Cyclone IV E, Quartus Prime + ModelSim, Verilog/VHDL.
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.