riscv: multikernel doorbell (IMSIC identity or SBI IPI convention) #28

Part of the RISC-V port. Equivalent of MULTIKERNEL_VECTOR + mk_arch_send_ipi() on x86.

Two mechanisms depending on the platform:

• IMSIC systems: reserve a system-wide interrupt identity IMSIC_MK_ID (next to IMSIC_IPI_ID = 1 in irq-riscv-imsic-state.c, must be excluded from the allocator on every kernel). mk_arch_send_ipi(hartid) = 32-bit write of IMSIC_MK_ID to the target hart's S-mode interrupt file, whose physical address is computed from the IMSIC geometry in the DTB (imsic_get_global_config() layout). Crosses kernels with no shared state. Handler: imsic_handle_irq() dispatches IMSIC_MK_ID to generic_multikernel_interrupt().
• SBI IPI / ACLINT SSWI systems: the only IPI is the single sip.SSIP bit. Linux multiplexes IPI types through ipi_mux, whose per-CPU bitmask lives in the receiver's memory, which the host cannot set. Convention: an SSIP with no ipi_mux bits pending is a multikernel doorbell; add a hook in sbi_ipi_handle() (arch/riscv/kernel/sbi-ipi.c) that drains the ring in that case. Sender: sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, 1, hartid, ...) directly, since sbi_send_ipi(cpu) takes a logical CPU and cannot address foreign harts.
• Filter foreign doorbells the way x86 filters foreign stop NMIs.

Test: host <-> spawn multikernel_send_ipi_data() round-trip on QEMU with and without aia=aplic-imsic.