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arm64: spin-table fallback park loop for platforms without PSCI #19
Description
Part of the arm64 port. Only needed for DT platforms without EL3 firmware (enable-method = "spin-table"). Do not build the common path around this.
Where PSCI is absent, a minimal software park is required:
- Host parks a CPU with
cpu_install_idmap()+cpu_soft_restart(el2_switch, park_pa, mailbox_pa, mpidr, 0)(arch/arm64/kernel/cpu-reset.S), the path kexec already uses, including the hyp-stubHVC_SOFT_RESTARThandling. Requires the samecpu_hyp_reset()orderingmachine_kexec()has. - Park loop, MMU off, in a host-owned page (~30 instructions): load mailbox, compare MPIDR,
wfe, on matchmov x0, dtb; br entry. With the MMU off data accesses are Device-nGnRnE, so no page tables and no cache maintenance in the loop; the writer needsdcache_clean_poc+sev. - The spawn boots its secondaries with stock
smp_spin_tableand acpu-release-addrpointing at the host-owned mailbox. - Confirm-parked = the CPU has written its MPIDR into a per-CPU "parked" word.
- No forced halt beyond a plain SGI.
Activity
congwang-mk commentedon Sep 21, 2026
Closing as won't-do. This fallback only matters on machines without PSCI, and the servers multikernel targets all have it: Arm's server firmware requirements (SystemReady/SBBR) mandate PSCI, which is the path the arm64 port already uses to hold, start and stop CPUs.
The machines that boot with spin-table are embedded boards, and they mostly lack the GICv3 and ITS the port depends on for the doorbell, tenant mode and MSI routing. Supporting them would also mean rebuilding the software CPU lifecycle (park loop, mailboxes, confirm-parked) that arm64 gets to skip, with nothing available to test it on.