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JLC library tooling draws package body outlines on the unassigned EasyEDA layer 0 (e.g. the 14mm outline of TFBGA-265 on C114407), which aborted installation with "Cannot convert graphics on unsupported layer 0". Layer 0 is now treated like the other internal documentation layers (99/100/101): its graphics are omitted from the footprint output but still bound the courtyard, and they no longer block substitution with a KiCad built-in footprint.
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Problem
jlc-cli install C114407(STM32H743XIH6, TFBGA-265) fails with:Root cause
JLC library tooling draws the package body outline (the 14 mm
RECTof the TFBGA-265 footprint) on the unassigned EasyEDA layer 0. The footprint converter'sKI_LAYERSmap has no entry for it, sogetLayer(0)throws and aborts the whole installation.Fix
Treat layer 0 like the other internal EasyEDA documentation layers (99/100/101):
INTERNAL_LAYER_IDS = [0, 99, 100, 101]used by all six graphic generators (TRACK/CIRCLE/ARC/RECT/TEXT/SOLIDREGION) — layer 0 graphics are omitted from the output but still bound the courtyard, consistent with existing doc-layer behaviorcanSubstituteStandard, so a 2-pad passive with a layer 0 doc graphic can still map to a KiCad built-in footprintTruly unknown layers keep failing loudly as before.
Testing
packages/coreconverter tests: 101 pass;cli+mcptests: 37 pass; typecheck clean across all packagesjlc-cli install C114407now succeeds and writes the 265-padTFBGA-265_L14.0-W14.0-P0.80-TL_STM32H743XIH6footprint to the KiCad libraryIncludes a changeset (
@jlcpcb/core: patch).