Repository navigation
T48: a higher clock is not higher throughput - #838
Merged
Merged
Conversation
An operator replaced by an iterative one of depth 1 raises the clock and multiplies the cycle count. Break-even is 1 + k < 2 * f_iter / f_direct. Measured by real place-and-route (nextpnr-ice40, hx8k, fan-in 8): the Fibonacci-step scale reaches 144.80 MHz in 425 cells against 69.21 MHz in 1098 for the multiplier -- smaller AND twice the clock. Break-even is k = 3.18, and the deployed scale needs |k| = 8, so the multiplier is 2.15x faster per element. The refusal names the fabric: iCE40 has no DSP blocks, so the multiplier arm is maximally penalised; on a part with DSPs it is smaller in LUTs. Audits run locally: RU and EN PASS, 27 routes.
github-actions Bot
added a commit
that referenced
this pull request
Aug 18, 2026
T48: a higher clock is not higher throughput (#838) An operator replaced by an iterative one of depth 1 raises the clock and multiplies the cycle count. Break-even is 1 + k < 2 * f_iter / f_direct. Measured by real place-and-route (nextpnr-ice40, hx8k, fan-in 8): the Fibonacci-step scale reaches 144.80 MHz in 425 cells against 69.21 MHz in 1098 for the multiplier -- smaller AND twice the clock. Break-even is k = 3.18, and the deployed scale needs |k| = 8, so the multiplier is 2.15x faster per element. The refusal names the fabric: iCE40 has no DSP blocks, so the multiplier arm is maximally penalised; on a part with DSPs it is smaller in LUTs. Audits run locally: RU and EN PASS, 27 routes.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
From trinity-fpga#591, the first real place-and-route in this work.
T48 — a higher clock is not higher throughput when the cheaper operator needs more cycles. Replacing an operator with an iterative one of depth 1 raises the achievable clock and multiplies the cycle count. Throughput per element is
(1+k)/f_iteragainst2/f_direct, so the iterative form wins only while1 + k < 2·f_iter/f_direct.Measured — nextpnr-ice40, hx8k ct256, fan-in 8:
Smaller and twice the clock — and the break-even is k = 3.18. The deployed scale is
α = mean|W| ≈ 0.02, i.e.log_φ 0.02 = −8.13, so a real layer needs|k| = 8: the multiplier is 2.15× faster per element despite half the clock.The refusal names the fabric: iCE40 has no DSP blocks at all, so the multiplier arm is maximally penalised here; on a part with DSPs it is smaller in LUTs than the iterative arm. An unrolled or barrel variant would trade the cycles back at more area and is not built.
Ratchet 179/26 against baseline 184/27, no file gained. Audits run locally: RU and EN PASS, 27 routes.