🔬 TODO 2: Trinity FPGA Level 2 — Full Inference Pipeline + Hardware Validation

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🔬 TODO 2: Trinity FPGA Level 2 — Full Inference + Hardware Validation

Предыдущий этап: #127 Level 1 — COMPLETE (8/8 implemented)

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✅ IMPLEMENTATION REPORT (2026-03-11)

TRINITY FPGA VERDICT v3.0
========================
EXP-2  (Token Embedding):       ✅ DONE — embedding_lookup_512.v, 6 tests, export_weights.zig 4/4 PASS
EXP-3  (LM Head Integration):   ✅ EXISTING — hslm_timemux_top.v + hslm_full_top.v (Level 1)
EXP-6  (Power Measurement):     ✅ CODE DONE — power_modes.v (5 modes, debounce, UART report, XDC)
EXP-11 (Synthesis Validation):  ✅ CODE DONE — Makefile.validate (10 targets, summary table)
EXP-12 (Paper Update):          ✅ DONE — draft.md Sections 5.2-5.5 rewritten, Appendix A expanded

BUILD: 5/5 DONE

⚠️  BLOCKER: make -f Makefile.validate validate-all requires Yosys on host
⚠️  BLOCKER: EXP-6 power numbers require USB power meter on real hardware

PAPER STATUS: estimates → real data PENDING synthesis run

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🚨 Critical Blockers (НУЖНЫ РЕАЛЬНЫЕ ДЕЙСТВИЯ)

BLOCKER #1: Yosys Synthesis

# Запустить на машине с Yosys:
cd fpga/openxc7-synth
make -f Makefile.validate validate-all
# Ожидаем: реальные LUT/BRAM/timing для всех 10 модулей
# Результат → benchmarks/synthesis_results.md

Разблокирует: latency claim (28.5ms → 14ms), LUT utilization paper table

BLOCKER #2: USB Power Meter

# Подключить USB power meter (J7-t / UM25C / аналог)
# Программировать power_modes.v → битстрим → FPGA
# Измерить 5 режимов: idle / LED / 1-block / 4-block / pipeline
# Заполнить: papers/trinity-fpga/power_results.md

Разблокирует: $0.86/tok/s/W claim → принятие paper reviewerами

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📊 Delivery Table

Agent	Задача	Артефакт	Статус
F	EXP-2: Token Embedding	embedding_lookup_512.v, embedding_lookup_tb.v (6 tests), export_weights.zig	✅ DONE
G	EXP-3: LM Head	hslm_timemux_top.v + hslm_full_top.v	✅ EXISTING (Level 1)
H	EXP-6: Power firmware	power_modes.v (5 modes, debounce, UART report, XDC)	✅ CODE DONE
I	EXP-11: Synthesis	Makefile.validate (10 targets, deps check)	✅ CODE DONE
J	EXP-12: Paper	draft.md 5.2-5.5 rewritten, Appendix A expanded	✅ DONE

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📊 Benchmark Status

Метрика	Baseline	Level 1	Level 2 цель	Статус
BRAM36	128/135	128/135	135/135	⏳ pending synth
LUT	6864	~7214	< 15K	⏳ pending synth
DSP48	0/240	0/240	0/240	⏳ pending synth
Latency	28.5ms	28.5ms	< 16ms	⏳ pending synth
E2E autoregressive	❌	❌	✅	⏳ needs synth
Power	~0.5W est	~0.5W est	real W	⚠️ needs hardware
Token Embedding	❌	❌	512 tokens	✅ code done

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🌳 Technology Tree — Level 3

Level 3 (разблокируется после синтеза):
  🔥 EXP-7: Artix-7 200T (365 BRAM36, 11 blocks, 1.9M weights)
      → только смена PART в Makefile, нужна плата ~$50-80
  🧪 EXP-8: Attention (уже код есть, нужен BRAM от SPI Flash offload)
      → SPI Flash (EXP-9) уже реализован → перенести веса → 32 BRAM36 для Q,K,V

Paper submission:
  → после power measurement + synthesis validation

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⚡ Следующие действия

1. [НЕМЕДЛЕННО] make -f Makefile.validate validate-all на машине с Yosys
2. [НЕМЕДЛЕННО] Запрограммировать power_modes.v на железо + USB power meter
3. После синтеза: заполнить реальные цифры в benchmarks/synthesis_results.md
4. После power: заполнить papers/trinity-fpga/power_results.md
5. Финал: git pull && git merge && git add -A && git commit -m "feat: Level 2 full inference pipeline" && git push

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Статус: 🟡 CODE COMPLETE → ⚠️ PENDING HARDWARE VALIDATION

Связано с: #127 (Level 1)

/cc @gHashTag

[gHashTag]

✅ JTAG Switcher — 9/9 Subcommands WORKING

Root Cause Fix

• bitrev() on CFG_OUT (commit 605442f1c): all JTAG reads returned garbage because TDO bytes weren't bit-reversed. CPLD 0xFFFE was NOT hardware — it was this bug.

Verify Fix — UG470-Compliant Frame Comparison

Per UG470, without Vivado .rbd/.msd files, exact verify match is impossible. New verify implementation:

• Finds FDRI write command in .bit → extracts frame data with correct alignment
• Skips 1 pad frame in readback (101 words = 404 bytes)
• Masks ECC word (word feat(agent): Ralph sleep-wake daemon — native Zig binary #50 per frame) — volatile
• Tracks BRAM frames separately — volatile after startup
• Reports logic vs BRAM vs ECC mismatches independently
• 333 mismatches → ~0 logic mismatches (rest are ECC + BRAM = expected)

Status Table

Subcommand	Status	Notes
status	✅ PASS	STAT=0x401079FC, DONE=1
idcode	✅ PASS	0x13631093 XC7A100T
dna	✅ PASS	57-bit device DNA
reg	✅ PASS	Any register 00-1F
readback	✅ PASS	1.5 MB frame data
write	✅ PASS	3.6 MB, DONE=1
verify	✅ PASS	Frame-level with masking
probe	✅ PASS	Bitmask 0xF
debug	✅ PASS	6-step diagnosis

JTAG switcher subtask complete. Hardware read/write/verify fully operational.

[gHashTag]

Requires FPGA hardware (XC7A100T Artix-7). Not actionable without physical hardware.