feat(vsa): ternary matmul kernel — XOR + popcount, 0 DSP

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Summary

Closes #7 (Phase 2)

Ternary matrix-vector multiply over VSA ALU — pure LUT logic, zero DSP48 blocks.

Verilog (fpga/vsa/)

• vsa_matmul.v — 64×64 sequential ternary matmul using VSA bind (element-wise ternary multiply) + popcount for signed dot product. Register-based weights, combinational bind+popcount, 1 row/clock latency.
• tb_vsa_matmul.v — self-checking testbench: 64/64 PASS (iverilog 13.0)

Rust (rings/FP-01/)

• Gf16Binary — parser for igla_champion_gf16.bin format (magic 0x47463136, multi-tensor)
• TernaryWeightConverter — GF16 u16 → ternary {-1, 0, +1} quantization with configurable threshold
• Packed trit format — 2 bits/trit (same encoding as vsa_bind.v), 32 trits/u64 word
• write_verilog_mem() — generates $readmem-compatible .mem files for BRAM init

Verification

• cargo test --workspace: 21/21 PASS (8 FP-00 + 9 FP-01 + 4 FP-02)
• iverilog tb_vsa_matmul: 64/64 PASS
• cargo clippy --workspace: 0 warnings

Architecture

x_vec[64 trits] ──┐
                  ├── bind (ternary multiply) ── popcount(+1) - popcount(-1) ── y[j]
W[j][64 trits] ───┘         (XOR-like LUT)           (add/sub tree)
                              0 DSP48                   0 DSP48

φ² + φ⁻² = 3 | TRINITY