What is wrong
Seven workflows run bbaexport.py with no chipdb cache at all: bufr-divide-probe, fpga-hslm-bitstream, iddr-golden-diff, iddr-vivado-diff, openxc7-vs-vivado-openxc7-half, part-coverage and router-vcc-reducer.
Some of them have a reason. openxc7-vs-vivado-openxc7-half builds nextpnr from source and says the chipdb "must come from the SAME tree as the binary that reads it", so its key would have to be the nextpnr source revision, not the image digest. The others use other parts (xc7a35tcsg324-1, xc7a100tfgg676-1, a part matrix). The composite action needs to take the part, and optionally a source revision.
Fix
- Extend the composite action with
part and an optional rev input.
- Review each of the seven: cache it, or record why not in the workflow.
Part of #851.
What is wrong
Seven workflows run
bbaexport.pywith no chipdb cache at all: bufr-divide-probe, fpga-hslm-bitstream, iddr-golden-diff, iddr-vivado-diff, openxc7-vs-vivado-openxc7-half, part-coverage and router-vcc-reducer.Some of them have a reason. openxc7-vs-vivado-openxc7-half builds nextpnr from source and says the chipdb "must come from the SAME tree as the binary that reads it", so its key would have to be the nextpnr source revision, not the image digest. The others use other parts (xc7a35tcsg324-1, xc7a100tfgg676-1, a part matrix). The composite action needs to take the part, and optionally a source revision.
Fix
partand an optionalrevinput.Part of #851.