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feat(verified): PoC static region + two compatible slots, sealed A -> B frontier (#6656) - #6705
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…6655) specs/verified/frontier.t27 walks nodes in topological order once and gives each REUSE or the reason to rebuild, using reuse.t27 per node. An edge that is forward, self or out of range fails closed (REBUILD_MISSING). 9 tests (diamond + bystander: unchanged, leaf, shared base, one side, toolchain, failed import, two negative controls, determinism) pass under zig test on the Railway lab with master t27c 1c0299f; 5/5 mutants killed; gen-verilog and gen-c exit 0; seal --verify all hashes MATCH. Closes #6673 Refs #6655 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… B frontier (#6656) specs/verified/poc/: static_counter.t27 (static region, clocked counter), a/slot.t27 and b/slot.t27 (two implementations of module PocSlot with the same on_comb signature), run.t27 (the A -> B step judged by frontier.t27). Evidence from master t27c 1c0299f + zig 0.16.0 on the Railway lab: seal --verify all hashes MATCH for all four; gen-verilog `module PocSlot` headers of A and B byte-identical; A and B spec_hash differ; run.t27 4/4: static REUSE, slot REBUILD_SPEC, new toolchain reuses nothing, injected failure has one fingerprint, hardware UNPROVEN. No device was programmed. Closes #6677 Refs #6656, #6655 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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This was referenced Oct 6, 2026
Phase G (#6655): FPGA region identity and partial-image admission in specs/verified/region.t27
#6716
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Replaces #6678 (closed unmerged: same stacked-base deletion as #6674/#6690 when #6671 merged). Same content, cherry-picked 1c8a29b. Merge after the frontier replacement PR -- run.t27 uses verified::frontier.
Closes #6677
Phase 0 MVP slice of #6656 (child of epic #6655).
specs/verified/poc/: static_counter.t27 (static region) + a/slot + b/slot (two compatible PocSlot implementations; the dirs give distinct seal names) + run.t27 running the frontier over observed parts. Seals: A and B share the port list but differ in spec and Verilog hashes; the injected failure normalizes to the same assertion in both. Hardware stays UNPROVEN -- no device transcript yet.
Railway lab, master t27c: 4/4 zig tests, seal hashes MATCH, Verilog port lists identical between A and B.
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