S11: the FPGA adapter contract and the first device receipts (Refs #3573)

[dmitrii-f-t27]

RU: контракт FPGA-адаптера S11 — версия, входы с правилом полного IDCODE, конфигурация, 8 различных ошибок, квитанция trinity.fpga-receipt.v1 и граница dry-run/flash. Первые device-квитанции: золотой chunk 320/320 бит-в-бит в обоих форматах на AX7203. Владелец (Dmitrii Vasilev) одобрил открытие этого PR 2026-09-27.

Refs #3573. Refs gHashTag/trinity#588. Refs dmitrii-f-t27/trinity-memory#66. S11 of gHashTag/trinity#988, in the S05 shape (S01–S06 merged 2026-09-12 via #3581 and siblings).

What

• specs/fpga/adapter.t27 — the versioned contract: inputs (bitstream sha256 tied to provenance, board identity under the full-IDCODE rule: the full 32-bit value recorded beside openFPGALoader's nibble-dropped print, so a masked match never passes), configuration (flasher, cable, sram/flash target), eight distinct error statuses (wrong_version, hash_mismatch, bitstream_absent, bitstream_empty, placeholder_command, idcode_mismatch, transcript_missing, dry_run_as_device), the trinity.fpga-receipt.v1 receipt schema and the dry-run/flash boundary — a build-only record is hardware: false and never carries a result line; a device receipt always carries the bitstream sha256, the full IDCODE, the transcript sha256 and an HW RESULT line. The two laws of [spec][Trinity S11] Specify adapters to existing training, network and hardware projects #3573 hold throughout: no hardware run is inferred from synthesis; physical acceptance is tied to a recorded device and transcript.
• tools/trinity_fpga_adapter.py — check (receipts held to the contract, parsed from the spec itself) and self-check (each of the eight defects planted once, each refused by its own status: 8/8).
• conformance/trinity/fpga_adapter.json — the receipts: four device records (the golden chunk in dense5 and baseline2, 320/320 Y lines bit-exact each; the weights-per-second runs, 12/12 each) and one dry_run build record, each with bitstream sha256, provenance (commit, routed Fmax, verdict), full IDCODE 0x13636093 beside the printed 0x3636093, and transcript hashes.
• Card specs/trinity/capabilities/fpga.adapter.t27 (trinity/fpga.adapter, OWNER_REPO dmitrii-f-t27/trinity-memory, WORK_PACKAGE S11, EVIDENCE measured), OWNERS/README rows, two seals, and the docs/now entry.

Measured

ALINX AX7203 (XC7A200T, IDCODE 0x13636093): BitNet b1.58 2B4T layer-0 q_proj rows 0–319 (819,200 weights) read from DDR3 at 240 MHz through the UART loader, decoded and dotted on the device — every Y line equal to the t27/C reference, both formats (first rows −2561, 2660, −52, −2385). The receipts carry the build records of the bitstreams that ran (routed Fmax 64.32 MHz PASS at 60 MHz target).

Verification

python3 tools/trinity_fpga_adapter.py check → 5/5 receipts pass. self-check → 8/8 defects raised by their own status; the clean dry-run receipt passes. tri hooks pre-commit passes on the rebased branch (the NOW entry follows the current gate format). The upstream Bridge change of #64 may ride separately — this PR does not include it.

What this does not claim

• No hardware run is inferred from synthesis (the build record is a separate dry_run receipt).
• The receipts' bitstreams were built on the bench, not in CI (Tier-E's CI-run URL waits on the bitstream-publishing decision — decided: never shipped as artifacts).
• Only the AX7203 board is evidenced; one flasher (openFPGALoader) is exercised.
• The board spec question (cite trinity-fpga's ax7203_full.t27 by identity, or add one here) is left open as listed in [upstream] S11 in gHashTag/t27: FPGA adapter contract, bitstream path, dry-run/flash boundary, device receipt dmitrii-f-t27/trinity-memory#66's open questions.

Do not merge without the owner's approval

The owner's review is requested; per #3573's and the epic's rules this PR is not merged without it.

🤖 Generated with Claude Code

[dmitrii-f-t27]

The four red checks (Corpus ratchet, Documented t27c subcommands exist, coverage, duplicate-bodies) are pre-existing on master itself — the check-runs of the master commit this PR is rebased onto (8445945) list exactly these four as failures. This is the "pre-existing master failures excepted" clause of the S11 issue (dmitrii-f-t27/trinity-memory#66): the branch's own gates pass (tri hooks pre-commit, trinity_fpga_adapter.py check 5/5, self-check 8/8, and the rest of the CI matrix is green on this PR).