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fix(codegen): lower a return nested inside an if block as a real early exit (Refs #1697) - #1798
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…y exit
gen_verilog_fn_body's guarded-return rewrite (if(cond){...return} <rest>
=> if(cond){...} else {<rest>}) only fired at the top level of a function
body. A `return` nested inside the then-block --
`if(outer){ ...; if(inner){return A} return B }` -- fell through to two
sequential Verilog function-name assigns, and last-write-wins silently
discarded the guarded value A. This is the root cause of the GF-T
negative-zero cancellation bug (sadd(-1.0,+1.0) returned the fall-through
magnitude instead of 0), which last cycle was only worked around at the
spec level in five signed specs.
Fix: emit the guarded then-block via a recursive gen_verilog_fn_body call
so a nested `if(inner){return A} return B` is itself lowered as an
if/else early exit rather than two sequential assigns.
Adds regression test nested_return_lowers_as_early_exit. Reseals
FROZEN_HASH. 1536 unit tests pass; 0/33 ternary seals change.
Refs #1697
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-08-06 15:04:22 UTC
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What
Root-cause compiler fix for the GF-T negative-zero cancellation class found in the previous cycle.
gen_verilog_fn_body's guarded-return rewrite (if(cond){…return} <rest>→if(cond){…} else {<rest>}) only fired at the top level of a function body. Areturnnested inside the then-block —— fell through to two sequential Verilog function-name assigns (
fn = A;thenfn = B;), and last-write-wins silently discarded the guarded valueA.This is the root cause of
sadd(-1.0, +1.0)returning the fall-through magnitude (a wrong negative zero) instead of0, which was only worked around at the spec level last cycle in five signed GF-T specs.Fix
Emit the guarded then-block via a recursive
gen_verilog_fn_bodycall, so a nestedif(inner){return A} return Bis itself lowered as anif(inner) A else Bearly exit rather than two sequential assigns.Verification
sadd-shapedf):f(5,5)now= 0(was fall-through),f(7,5) = 65538,f(3,5) = 99— all correct undericarus-simulate.nested_return_lowers_as_early_exit.Seal impact
A small minority (~2%, all latent-bug specs) now emit corrected Verilog with stale-but-non-blocking seals (seal-staleness only warns). Documented follow-up reseal — not a merge blocker.
Refs #1697
🤖 Generated with Claude Code