feat(gen-verilog): spec-first ternary designs synthesize to real Artix-7 hardware (on_clock/on_comb data ports) (#1764)

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Makes the spec-first ternary stack real, synthesizable FPGA hardware — the on-hardware MVP path for #1764. Self-consistent and buildable (compiler.rs sha == FROZEN_HASH); supersedes the externally-force-pushed, non-compiling branch of #1782.

The problem this solves

The stack was only ever simulated (iverilog). Running yosys synth_xilinx for the first time showed every design synthesized to zero cells: the fixed module interface (clk,rst_n,en,ready) had no data ports, so all compute drove nothing observable and the synthesizer dead-code-eliminated it. iverilog testbenches had been reaching inside the module to call the Verilog functions hierarchically.

What's here (all Refs #1764)

1. Clocked on_clock process — registered module var state with reset + en gating (always @(posedge clk), nonblocking <=).
2. Output data ports — a clocked module's scalar vars are exposed as output reg; ClockedCounter → 8 FDCE + 2 CARRY4.
3. Streaming input ports + a streaming ternary MAC — on_clock params become input data ports; stream_ternary_mac.t27 accumulates bit-exact dot27 across cycles → 32 FDCE + a LUT adder-tree.
4. on_comb combinational data interface — params → input ports, return → output wire result; makes the combinational half of the stack real hardware (comb_ternary_dot.t27 → ~162 LUT6, no FFs).
5. Combinational BitNet neuron — comb_bitnet_neuron.t27 = quantize(dot27(a,b)) in one module → ~319 LUT + 2 CARRY4, 0 FF.
6. docs/SYNTH_REPORT.md — measured Artix-7 cost of every design (a neuron is ~0.24% of the XC7A200T).

Verification

• Every new module: iverilog cross-check vs an independent reference + yosys synth_xilinx (asserts real FFs/LUTs), in bootstrap/tests/{clocked_counter,stream_ternary_mac,comb_ternary_dot,comb_bitnet_neuron}.rs.
• Seal-neutral: seal --verify Verilog byte-identical on all existing ternary specs (new interface behavior is gated on on_clock/on_comb fn names). FROZEN_HASH resealed. 1506 unit tests pass.

Notes

• Branch is off an older master and needs a rebase onto current master: resolve bootstrap/src/compiler.rs by taking master's version + re-applying the additive port edits (a plain merge silently mis-merges that ~30k-line file into non-compiling code — this is what broke feat(gen-verilog): clocked on_clock process — first sequential spec-first design (#1764) #1782's branch).
• Known follow-up: a single-module streaming neuron (registered y=quantize(acc)) needs a dead_store_elim soundness fix (don't eliminate writes to module vars exposed as output ports) — not seal-neutral, needs a repo-wide reseal sweep (owner decision).

🤖 Generated with Claude Code

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Landing status (verified this cycle): good news and a blocker that isn't ours.

• My cycle-1 clocked construct (on_clock, gen_verilog_clocked_fn, clocked_nonblocking) already landed on master — identical to this branch's version.
• The rest of this PR applies cleanly onto current master: I extracted the output-ports/input-ports/on_comb compiler delta and git apply --3way'd it onto origin/master (one trivial conflict — master's safe_name vs my node.name in gen_verilog_var, resolved by keeping both), added the additive spec/test/seal files, resealed, and it cargo builds clean. So this work is master-ready.
• The blocker is a master codegen regression, not this PR: current master's gen-verilog emits a stray `endif with no matching `ifndef SIMULATION (visible even on a plain ternary_mac.t27 — 0 ifdef, 1 endif), which makes yosys reject every design and leaves 7 internal tests red (tests_w457_ram_style, tests_w458, tests_w459, tests_hir_pipeline_parity). This is the W458 guard-emission area that the in-progress repair-verilog-codegen-merge ([GOLD-RING] fix(compiler): restore declarations dropped by batch merge #1783 — master does not compile #1788) is working on.

Recommendation: once master's `ifndef/`endif guard emission is repaired and those 7 tests go green, this PR's port edits + specs drop in cleanly (build-verified). I did not push onto the broken base or touch the guard code under active repair.

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Superseded by #1791, which landed the spec-first hardware stack (data ports + BitNet + GF-T + RNE) onto the now-unblocked master (#1790). All specs re-verified on master's compiler.