Next wave after #1323 (W409).
W409 generalized the SPI flash read-transaction proof to a per-OSCFSEL lookup for OSCFSEL = 0..7 and tightened the tri fpga measure-cclk --validate duty-cycle guard using the N25Q128 t_CL / t_CH limits. The real P12 CCLK capture is still blocked because P12 is not wired to ADBUS4. W410 should pick the strongest remaining work:
Recommended bundle: Variant A + C
- Variant A: retry the real P12 CCLK measurement once P12 → ADBUS4 (or DSLogic/scope) wiring is available.
- Variant C: physically boot
OSCFSEL=6,7 on the Wukong board to close the lookup table against silicon, and add a measured-duty formal lemma linking a captured (frequency, duty) pair to transaction_satisfies_flash_spec.
If P12 wiring is still unavailable, fall back to Variant C alone. If CI automation is the priority, pick Variant B (relay-controlled cold-POR + JTAG isolation).
See docs/reports/FPGA_LOOP_COOPERATION_W410_2026-07-04.md for full details.
/label ~wave-loop
/assign @gHashTag
🤖 Generated with Claude Code
Next wave after #1323 (W409).
W409 generalized the SPI flash read-transaction proof to a per-OSCFSEL lookup for
OSCFSEL = 0..7and tightened thetri fpga measure-cclk --validateduty-cycle guard using the N25Q128t_CL/t_CHlimits. The real P12 CCLK capture is still blocked because P12 is not wired to ADBUS4. W410 should pick the strongest remaining work:Recommended bundle: Variant A + C
OSCFSEL=6,7on the Wukong board to close the lookup table against silicon, and add a measured-duty formal lemma linking a captured(frequency, duty)pair totransaction_satisfies_flash_spec.If P12 wiring is still unavailable, fall back to Variant C alone. If CI automation is the priority, pick Variant B (relay-controlled cold-POR + JTAG isolation).
See
docs/reports/FPGA_LOOP_COOPERATION_W410_2026-07-04.mdfor full details./label ~wave-loop
/assign @gHashTag
🤖 Generated with Claude Code