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Add experimental Apple Silicon MPS backend for Pi0.5 - #232
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Route Apple Silicon through a dedicated BF16 eager frontend and MPS operation providers, reusing the shared Pi0.5 model traversal and checkpoint conversion. Keep CUDA/ROCm/Ascend routes unchanged and reject unsupported precision and graph options before loading native extensions. Add the apple dependency extra, CPU prompt embedding, hardware routing and pipeline parity tests, an SSD download and real-input smoke example, and stable API and deployment documentation. Validation on Apple M5 Pro 24 GiB, macOS 27.0.1, Python 3.12.14, torch 2.14.1: - Apple/shared-pipeline and AMD/NPU/prompt checks: 114 passed, 7 skipped. - Calibration helpers: 18 passed. Python install/import checks: 2 passed; the CUDA binary-presence test was excluded on this MPS-only host. - Full two-view, ten-step Pi0.5 checkpoint inference passes with finite 10x7 actions; fixed-noise outputs repeat exactly. Seven unnormalized action channels match the shared CPU BF16 implementation at cosine 0.99999818 (CPU GEMM accumulates in FP32 before BF16 rounding). - NVIDIA load-model smoke tests: 51 passed and 21 CUDA-runtime/extension failures, identical to the unmodified 81904ca baseline on this host. - git diff --cached --check passes. Weights, environments, caches and run artifacts remain outside the commit.
LiangSu8899
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Oct 20, 2026
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Thanks for the great work and the expanded support!! |
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Enjoy and have fun~ |
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FlashRT currently has no Apple Silicon inference route. This adds an experimental Pi0.5 BF16 backend using PyTorch MPS, reachable through
load_model(..., hardware="apple_mps")or automatic accelerator detection, without a CUDA/HIP extension build.The frontend, model binding and hardware providers follow the repository's separate ownership paths and reuse the existing Pi0.5 tensor traversal and safetensors conversion. The change also adds the
appledependency extra, CPU prompt embedding, explicit precision/graph rejection, stable API documentation, and an SSD download/real-input example. No CMake, native kernels, serving or training paths change.Validation
Apple M5 Pro, 24 GiB unified memory; macOS 27.0.1; native arm64 Python 3.12.14; PyTorch 2.14.1 with MPS available.
tests/test_load_model_use_fp8_kwarg.py: 51 passed and 21 failures caused by absent CUDA runtime/extensions. The unmodified81904cabaseline reproduces the exact same 21 failing cases in the same environment; no additional failing cases.git diff --checkpass. Weights, environments, download caches and generated run artifacts are excluded from the commit.Real-checkpoint smoke run
Checkpoint: Fisher-Wang/pi05-libero-pytorch, revision
ab107fbe6661e8abfec0f13dc27bfd3fafe24c69, a PyTorch conversion of OpenPI's Pi0.5 LIBERO weights with quantile normalization statistics. All five downloaded remote files passedhf cache verify; the tokenizer passed its expected MD5.Two camera views, ten denoising steps, ten-action horizon, and 147–150 state-prompt tokens:
All eight real camera/state observations produce finite
(10, 7)actions, and changing observations changes the output. A final smoke run after organizing the frontend/model/hardware modules also passed with identical numerical comparison metrics.Scope and limitations
This is BF16 eager execution with reusable buffers, time-modulation precomputation and SDPA. It does not implement
torch.compile, graph capture/replay, custom Metal kernels, MLX, FP8/FP4, temporal frame caching or other model families. The latency numbers are short local smoke measurements, not production statistics or CUDA graph replay comparisons.The CPU check shares the model traversal and converted BF16 weights; CPU GEMM accumulates exact BF16 operand values in FP32 and rounds to BF16 before bias addition. It checks device/provider numerics, not independent OpenPI accuracy or LIBERO simulator task success. CPU embedding storage and runtime overhead are additional to the reported MPS allocation.