Retracted the claim that a second TCM bank costs the data cache

[fdesbiens]

entry.S and readme_s32z280.txt both stated that enabling any second TCM bank removes all measurable data-cache benefit on this part, with five configurations as evidence:

ATCM only                      cache gain 24%
ATCM + BTCM                    cache gain  0%
ATCM + BTCM + CTCM             cache gain  0%
ATCM + BTCM at another base    cache gain  0%
ATCM + CTCM, BTCM disabled     cache gain  0%

Both concluded the cause was "not a particular bank, not its address, not the ECC preload — enabling a second bank at all". Both cited the Cortex-R52 and S32Z2 errata as not covering it, and offered a RAM pool shared between the LLC and the TCMs as the likely mechanism. A defect report went to NXP on that basis.

It was the benchmark

The benchmark was bimodal with respect to where its timing loop fell inside a 64-byte cache line — reporting either 24% or nothing at all for identical silicon (see #631). Every one of those five configurations was an edit to entry.S, so every one shifted the code that followed and moved the loop between modes.

Adding two nop instructions to entry.S reproduces the "second bank" figure exactly, to the digit. The report to NXP has been withdrawn.

Re-measured with the alignment sweep

loop offset in line	ATCM only	ATCM + CTCM
0	gain 0	gain 0
16	gain 0	gain 0
32	gain 240/1000	gain 240/1000
48	gain 240/1000	gain 240/1000

Indistinguishable. Enabling a second bank costs nothing measurable.

What the texts say now

The banks stay disabled, but for the ordinary reason that nothing in this example uses them — not because of a phantom regression. Enabling one is a single line, with the ECC preload before any read (TRM 6.2.2) and an MPU region as the only prerequisites, both already handled for ATCM.

The readme also states the general point, which outlasts the TCM detail: a single-figure timing result from this example cannot be compared across builds unless the timed loop's alignment is controlled, because almost any change shifts code. That is why the cache and handler measurements now sweep alignments.

Scope

Comments and documentation only; no generated code changes. Verified on the board anyway since entry.S was touched — six of six probes pass, sweep unchanged, all three targets build clean.