[release/10.0] Fix SIMD primitive zero initialization

[tannergooding]

Backport of #133100 to release/10.0

/cc @tannergooding

Customer Impact

• Customer reported
• Found internally

Reported in #133085. Zero-initializing a struct through a byref that the JIT can see is the address of a Vector128<T>/Vector256<T> local (Unsafe.As<Vector256<ulong>, S>(ref v) = default;) produces a SIMD store whose source is an integer zero constant. With optimizations that lowers to vmovq ymm0, rax (C4 E1 FD 6E C0), which has no valid VEX.256 encoding, so the process dies with ExecutionEngineException: Illegal instruction; at Tier0 the same method fails to compile and throws InvalidProgramException. Expected behavior is a SIMD zero (vxorps) in both modes.

The pattern shows up in code that reinterprets vector locals as multi-limb structs, and there is no compile-time diagnostic — it fails at runtime on any AVX-capable x64 machine.

Regression

• Yes
• No

Not a regression in 10.0 — .NET 9 fails the same way. The bad tree dates to the assignment rationalization work in #85585 (53b4cd0912d), where the legacy GT_ASG path updated gtOp2 but the rationalized store path never updated Data().

Testing

New regression test src/tests/JIT/Regression/JitBlue/Runtime_133085, covering Vector128<ulong> and Vector256<ulong> in both FullOpts (AggressiveOptimization) and Tier0. It reproduces the illegal encoding / InvalidProgramException without the fix and passes with it.

Missed previously because TryPrimitiveInit looked correct in isolation — it built the SIMD zero node and assigned it to m_src — and no existing test zero-initialized a SIMD local through a reinterpreted struct view, so nothing exercised the path where the store's data operand still had to be replaced.

Risk

Low. Two lines in TryPrimitiveInit, reached only when a block zero-init of a SIMD-typed local is converted into a primitive store. It makes the store's data node match the store's type, which is what the transform already intended; every other case was already consistent.

This is a manual backport: the cherry-pick conflicted only because the member is named m_comp on release/10.0 rather than m_compiler. The change is otherwise identical to #133100.

Note

This pull request description was generated with GitHub Copilot.

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Copilot review overview

🟢 Approval recommended

The JIT fix correctly updates the store operand for SIMD zero-inits and the added regression test directly covers the reported failure modes.

Review tier: Lite
Findings: None

What changed in this PR

Backports the fix for a CoreCLR JIT morphing bug where a SIMD-typed local block zero-init could be converted into a primitive SIMD store while still carrying an integer-zero source node, leading to invalid codegen (illegal instruction) or Tier0 compilation failure; adds a targeted JIT regression test to prevent recurrence on release/10.0.

Changes:

• Fix MorphInitBlockHelper::TryPrimitiveInit to replace the store’s data operand when retyping an integral zero-init into a SIMD zero.
• Add a new JIT regression test (Runtime_133085) covering Vector128<ulong> and Vector256<ulong> in both AggressiveOptimization (FullOpts) and Tier0 scenarios.
• Add test project configuration to run with tiered compilation enabled and in isolated process mode.

File	Description
src/​coreclr/​jit/​morphblock.cpp	Ensures SIMD zero-init transforms update the store’s Data() operand to a SIMD-typed zero node (and marks it morphed) before converting to GT_STORE_LCL_VAR.
src/​tests/​JIT/​Regression/​JitBlue/​Runtime_133085/​Runtime_133085.cs	Adds regression coverage for zeroing a SIMD local via a reinterpreted struct byref under both FullOpts and Tier0.
src/​tests/​JIT/​Regression/​JitBlue/​Runtime_133085/​Runtime_133085.csproj	Adds the test project with process isolation and a tiered compilation environment variable required to exercise the Tier0 path.

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[JulieLeeMSFT]

@EgorBo, please review this servicing PR.

[JulieLeeMSFT]

@tannergooding, please check a test failure.

[tannergooding]

Test failures are unrelated, they are the httplistener timeouts and quic failures that have since been fixed in main