Filing an issue on @stephentoub's behalf:
int Count() => Vector<int>.Count;
Vector<int> Add(Vector<int> a, Vector<int> b) => a + b;
Codegen on a CPU with AVX2:
; Method Tests:Count():int:this (FullOpts)
mov eax, 8
ret
; Method Tests:Add
vmovups ymm0, ymmword ptr [r8]
vpaddd ymm0, ymm0, ymmword ptr [r9]
vmovups ymmword ptr [rdx], ymm0
mov rax, rdx
vzeroupper
ret Looks perfect, Vector<> is 256bit as expected. Now we if compile it without AVX (e.g. DOTNET_EnableAVX=0):
; Method Tests:Count():int:this (FullOpts)
mov eax, 4
ret
; Method Tests:Add
G_M64079_IG01: ;; offset=0000H
push rdi
push rsi
push rbp
push rbx
sub rsp, 88
mov rsi, rdx
G_M64079_IG02: ;; offset=000BH
movups xmm0, xmmword ptr [r8]
movups xmmword ptr [rsp+38H], xmm0
movups xmm0, xmmword ptr [r9]
movups xmmword ptr [rsp+28H], xmm0
xor edi, edi
G_M64079_IG03: ;; offset=001FH
test edi, edi
jl SHORT G_M64079_IG05
G_M64079_IG04: ;; offset=0023H
xor ecx, ecx
cmp edi, 4
setl cl
test cl, cl
jne SHORT G_M64079_IG06
G_M64079_IG05: ;; offset=002FH
mov rdx, 0x1EB80200008 ; ''
mov rcx, rdx
call [System.Diagnostics.Debug:Fail(System.String,System.String)]
G_M64079_IG06: ;; offset=0042H
lea rcx, bword ptr [rsp+38H]
movsxd rbx, edi
mov ebp, dword ptr [rcx+4*rbx]
test edi, edi
jl SHORT G_M64079_IG08
G_M64079_IG07: ;; offset=0051H
xor ecx, ecx
cmp edi, 4
setl cl
test cl, cl
jne SHORT G_M64079_IG09
G_M64079_IG08: ;; offset=005DH
mov rdx, 0x1EB80200008 ; ''
mov rcx, rdx
call [System.Diagnostics.Debug:Fail(System.String,System.String)]
G_M64079_IG09: ;; offset=0070H
lea rcx, bword ptr [rsp+28H]
add ebp, dword ptr [rcx+4*rbx]
test edi, edi
jl SHORT G_M64079_IG11
G_M64079_IG10: ;; offset=007CH
xor ecx, ecx
cmp edi, 4
setl cl
test cl, cl
jne SHORT G_M64079_IG12
G_M64079_IG11: ;; offset=0088H
mov rdx, 0x1EB80200008 ; ''
mov rcx, rdx
call [System.Diagnostics.Debug:Fail(System.String,System.String)]
G_M64079_IG12: ;; offset=009BH
lea rax, bword ptr [rsp+48H]
mov dword ptr [rax+4*rbx], ebp
inc edi
cmp edi, 4
jl G_M64079_IG03
G_M64079_IG13: ;; offset=00AEH
movups xmm0, xmmword ptr [rsp+48H]
movups xmmword ptr [rsi], xmm0
mov rax, rsi
G_M64079_IG14: ;; offset=00B9H
add rsp, 88
pop rbx
pop rbp
pop rsi
pop rdi
ret we get 128-bit Vector<T> (expected) and software fallback for all operators - it feels like they're marked as "needs avx2".
Filing an issue on @stephentoub's behalf:
Codegen on a CPU with AVX2:
Looks perfect,
Vector<>is 256bit as expected. Now we if compile it without AVX (e.g.DOTNET_EnableAVX=0):we get 128-bit
Vector<T>(expected) and software fallback for all operators - it feels like they're marked as "needs avx2".