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[VTA] VTA Compilation Script for Intel FPGA - #3494

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tmoreau89 merged 62 commits into
apache:masterfrom
liangfu:de10-nano_script
Jul 31, 2019
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[VTA] VTA Compilation Script for Intel FPGA#3494
tmoreau89 merged 62 commits into
apache:masterfrom
liangfu:de10-nano_script

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@liangfu

@liangfu liangfu commented Jul 4, 2019

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This PR compiles chisel implement of VTA for Intel FPGA, and its tested with de10-nano board from Terasic.

For the driver that works with the design is available in a separate PR #3394 .

@liangfu liangfu mentioned this pull request Jul 4, 2019
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@liangfu

liangfu commented Jul 4, 2019

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The design contains files with extensions .sdc .qpf .qsf .ipx .qsys, which are not allowed by Jenkins.

@tmoreau89

tmoreau89 commented Jul 4, 2019

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Thank you @liangfu; can you complement this PR with a compilation guide for Intel FPGA toolchain? The idea will be to extend this guide: https://docs.tvm.ai/vta/install.html and add a section for Intel FPGAs. Information would include what version of quartus is required etc.

@tmoreau89

tmoreau89 commented Jul 4, 2019

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the source for the guide is under docs/vta/install.md

@liangfu

liangfu commented Jul 4, 2019

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Sure, i could write a guide. To be comparable with PYNQ linux environment, I think it will be a long story with linux kernel compilation, bitbake configurations for custom Angstrom filesystem compilation (many components are missing in the distribution provided by Terasic), environment setup for cross compilation of CMA kernel module and the TVM libraries.

@tmoreau89

tmoreau89 commented Jul 4, 2019

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are you building your own linux kernel to get the RPC server to execute on the DE10 nano? If that is too long to describe in the install.md, can you prepare a google doc that describes the steps? It should be reproducible so other people can try the DE10Nano example themselves.

@liangfu

liangfu commented Jul 5, 2019

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That's because the linux kernel version in the disk image provided by Terasic is not compatible with the latest toolchain provided in Intel Quartus Prime. On the other hand, as requested, I would provide a document that describes sufficient details in setting up the running environment for VTA.

@tmoreau89

tmoreau89 commented Jul 5, 2019

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In that case I suggest to specify in the guide to install a previous version of Quartus prime to be compatible with that test platform.

@tmoreau89

tmoreau89 commented Jul 5, 2019

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Which one did you use to compile the test design?

@liangfu

liangfu commented Jul 6, 2019

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Currently, I'm using Intel Quartus Prime 18.0 Lite Edition. Let me first reform the scripts to use tcl script, complement this PR with a related document, and then I would inform you when this is ready to review.

@tmoreau89

tmoreau89 commented Jul 6, 2019

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Thank you I'll install it on my machine so I can reproduce the experiments.

@liangfu

liangfu commented Jul 8, 2019

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@tmoreau89 For now, both compilation script and the related documentation have been improved. I think one can easily generate the FPGA hardware for de10-nano with the written document and the compilation script. Please take a review.

@tmoreau89

tmoreau89 commented Jul 8, 2019

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Thank you @liangfu for the good work, I'll be reviewing it later today (I installed Quartus to reproduce the build).

@liangfu

liangfu commented Jul 29, 2019

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@tmoreau89 I think I have figured out the solution to generate .qsys file with a simple tcl script. In addition, I have also safely removed hps_io related pins, in order to minimize the design to focus on demonstrating VTA subsystem, and added a brief description on flashing SD card image. Please take another review.

tmoreau89
tmoreau89 requested changes Jul 30, 2019
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Comment thread vta/config/de10-nano_sample.json Outdated
Comment thread vta/hardware/intel/scripts/soc_system.tcl Outdated
Comment thread vta/hardware/intel/Makefile Outdated
Comment thread docs/vta/install.md Outdated
@tmoreau89

tmoreau89 commented Jul 30, 2019

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@liangfu, thank you for the great work; I'm glad you were able to minimize the auto-generated code footprint. I've added a few more comments before we merge that PR in. Thanks!

@liangfu

liangfu commented Jul 30, 2019

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Hi @tmoreau89 Thanks for the catch. I've addressed the review comments. Ready for next round of review.

@tmoreau89

tmoreau89 commented Jul 30, 2019

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Thank you @liangfu, I've made one more comment regarding the pkg_config.py file

tmoreau89
tmoreau89 requested changes Jul 30, 2019
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Comment thread vta/python/vta/pkg_config.py
tmoreau89
tmoreau89 reviewed Jul 30, 2019
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Comment thread docs/vta/install.md
@liangfu

liangfu commented Jul 31, 2019

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@tmoreau89 I've made some updates according to your review comments. Please feel free to let me know if there is anything else I should change in this PR.

@tmoreau89

tmoreau89 commented Jul 31, 2019

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Thank you for the contribution @liangfu ; this is a very exciting new direction for VTA/TVM!

@tmoreau89
tmoreau89 merged commit 83591aa into apache:master Jul 31, 2019
wweic pushed a commit to wweic/tvm that referenced this pull request Aug 9, 2019
@liangfu Wei Chen
[VTA] VTA Compilation Script for Intel FPGA (apache#3494)
607d05c 
* initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
wweic pushed a commit to neo-ai/tvm that referenced this pull request Sep 6, 2019
@liangfu Wei Chen
[VTA] VTA Compilation Script for Intel FPGA (apache#3494)
25a9e5c 
* initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
@tqchen tqchen mentioned this pull request Nov 8, 2019
Closed
tqchen pushed a commit to tqchen/tvm that referenced this pull request Mar 29, 2020
@liangfu @tmoreau89
[VTA] VTA Compilation Script for Intel FPGA (apache#3494)
3563047 
* initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
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@liangfu @tmoreau89 @vegaluisjose