[QDP] [feature] Pr5 implicit hadamard engine - #1390
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…tests - Expose encode_batch_tc through Rust core, PyO3, and Python backend - Fix IQP TC kernel: correct batch stride for ZZ params and raise FWT_SHARED_MEM_THRESHOLD to 12 for fused shared-memory path at N<=12 - Align ImplicitHadamardOzaki.cu with PR6 ldmatrix/alignment fixes - Add benchmark_pr5.py with --path fwt|tc|both (GPU-vs-GPU, no PyTorch) - Add test_iqp_tc_path.py smoke and normalization tests
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This pull request has been automatically marked as stale because it has not had any activity for 30 days. It will be closed in another 7 days if no further activity occurs. Thank you for your contribution. If you'd like to keep this open, leave any comment and the stale label will be removed. You can always ask for help on the Mahout dev mailing list or in GitHub Discussions. |
Related Issues
related #1385
Changes
Why
As established in the previous Kronecker Decomposition PR, a significant bottleneck in processing high-qubit circuits ($N \ge 14$ ) is memory. A traditional $O(4^N)$ matrix representation for the full Dense Hadamard transform completely exhausts modern GPU VRAM limits (causing Out-Of-Memory errors).
Even with the Kronecker Decomposition splitting the matrix into smaller blocks, generating and storing the explicit dense$H$ matrices in memory before applying Tensor Core operations is highly inefficient.
We need a way to perform Dense Matrix Multiplications (GEMM) on the Tensor Cores without ever storing the Hadamard Matrix in Global Memory.
How
This PR introduces the Matrix-Free Implicit Hadamard Ozaki Engine.
ImplicitHadamardOzakiEngineleverages the structural properties of the Hadamard matrix (.m16n8k32.s8Tensor Core instructions to perform the GEMM natively in hardware. Because the Hadamard values are alwaysnaive_implicit_hadamard_gemm_kernelplaceholder from PR 4 with the actual calls toengine.execute_implicit_hadamard.build.rsto drop the unsupportedsm_75(Turing) target fallback, as this specific Tensor Core instruction explicitly requiressm_80(Ampere) or higher.Benchmark Results
Environment: Dev Machine (NVIDIA GeForce RTX 4060 Laptop GPU)
Configuration: Batch size 64, 30 iterations, GPU-vs-GPU only (no PyTorch reference)
Script:
qdp/qdp-python/benchmark/benchmark_pr5.pyMeasured: 2026-06-10
Branch:
pr5-implicit-hadamard-engine(ba0376a4f)Encoding path options (
--path)fwtengine.encode(..., "iqp")— standard FWT dispatchtcengine.encode_batch_tc(...)— Ozaki Kronecker Tensor Core pathbothFWT vs Ozaki TC (after PR5)
Checklist