feat(precompute): migrate precompute mint to resolver; delete compute_sid (PR-4)

[zzylol]

Summary

PR-4 in the registry-allocated sid chain. After PR-1+2+3 (PR #190) the OTel sketch ingest path was on SeriesIdResolver; the precompute path was still content-addressing via compute_sid. This PR migrates the precompute path to the same resolver, making sid identity uniform across the system:

sid = registry-allocated u64 for (metric, attrs_fingerprint, agg_kind_canonical)

Matches the design goal: "single sid across asapcollector and asapquery-backend; precompute is just an extension of the OTel processors at the edge." Sketch sids and precompute sids now share one namespace, one AtomicU64::fetch_add counter, one WAL.

API change

SketchStore::ingest_precompute_for_agg_config takes a closure mint parameter:

pub fn ingest_precompute_for_agg_config(
    &self,
    mint_sid: impl FnOnce(&str, &str, &str) -> u64,  // NEW
    agg_cfg: &AggregationConfig,
    output: &PrecomputedOutput,
    accumulator: &dyn AggregateCore,
) -> Option<u64>

Closure receives (metric, attrs_fingerprint, agg_kind_canonical); callers pass |m, fp, ak| series_resolver.resolve(m, fp, ak). Keeps SketchStore free of any layer-inverted dependency on SeriesIdResolver (which lives in drivers::ingest).

Production wiring

• SketchStoreSink: gains series_resolver: Arc<SeriesIdResolver> field; constructor takes it; main.rs passes the shared resolver.
• BackfillWindowProcessor: gains optional series_resolver field via with_series_resolver(...) builder. When absent but sketch_index is set, processor logs a WARN and skips precompute writes (registry provenance still recorded — safe degradation, not a crash).
• BackfillService: plumbs the resolver through to its per-job processors via the same builder pattern.
• main.rs: wires the resolver alongside with_sketch_index for both sites (SketchStoreSink::new and BackfillService).

Tests touched

• capability_matching_tests.rs (2 sites): local resolver per fixture.
• schema_timeline_dispatch_tests.rs::seed_sum_at: thread-local resolver so multiple seeds share next_sid.
• lifecycle/eviction.rs::tests::write_one: thread-local resolver.
• test_utilities/engine_factories.rs (8 sites across 6 factory functions): ingest_with_fresh_resolver helper threads a per-factory resolver.
• output_sink.rs (2 inline tests): pass Arc::new(SeriesIdResolver::new()).

Deletions

• pub fn compute_sid (53 LOC, sketch_db/data/mod.rs).
• fn sketch_kind_tag + fn encode_sketch_config helpers.
• xxhash_rust::xxh64 import (no consumer left in this module).
• 4 unit tests at sketch_db/index/mod.rs:1130+ that exercised compute_sid directly.

Identity properties the deleted tests covered (metric/attrs/agg_kind discriminate sids, sketch vs precompute never collide, agg_type and parameters each contribute) are now covered structurally by:

• AggKind::canonical_string exhaustiveness over the enum.
• series_resolver::tests::distinct_agg_kinds_same_series_distinct_sids (the resolver's identity contract under Interpretation B).

What this PR does NOT change

• Sid wire format (still u64). Nothing on the agent side needs to change.
• WAL format (still v2 — agg_kind_canonical per record).
• Cargo.toml (no dep changes — xxhash_rust is still used by xxh3 in other code).

Stacking

Branched off feat/sid-registry-canonical (PR #190 head). PR #190 must merge first; this PR will then merge cleanly onto the new main. Reviewing the two PRs back-to-back makes the chain easier to follow.

Test plan

• cargo build -p data_plane (lib + bin) — clean
• cargo test -p data_plane --lib — 759/759 passing (was 763; -4 deleted hash tests)
• grep -rn "compute_sid\|compute_sketch_sid" data_plane/src — only historical comments remain
• Reviewer: confirm the closure-mint signature is the right separation (caller owns mint authority, SketchStore stays a pure storage facade).
• Reviewer: BackfillWindowProcessor skips writes when resolver is missing (logs WARN). Is this the right degradation, or should it fail loudly? Production wires both via main.rs so the path doesn't fire there; only tests can hit it.

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