perf: optimize repeated SIMD workloads

[geeknoid]

• Decode paired Base32 vectors with one validity reduction for cache-sized inputs.
• Compact forgiving Base64 whitespace with SIMD shuffles and clean-block copies.
• Keep Base64 parallel encoding serial below the measured 64 KiB cutoff.
• Validate long ASCII inputs with AVX2 while preserving the existing short path.
• Bound generic ASCII validity reductions so invalid data exits earlier.
• Unroll byte swapping across four vectors to expose independent work.
• Amortize growth in Base32, Base64, and hex append operations.

The append APIs previously used reserve_exact, which requested only enough capacity for the current chunk and could therefore reallocate and copy the accumulated output on nearly every call. Using reserve permits geometric over-allocation, trading bounded spare capacity for amortized growth and drastically fewer reallocations, while one-shot encode and decode APIs continue allocating their known final sizes exactly.

Representative native/static ABBA results from simd-benches:

Benchmark	Before	After	Delta
Base32 decode, 1.6 KiB	10.915 GiB/s	13.088 GiB/s	+19.9%
Base32 append encode, 10k chunks	1.005 GiB/s	1.747 GiB/s	+73.9%
Base64 append encode, 10k chunks	1.208 GiB/s	2.688 GiB/s	+122.6%
Hex append decode, 10k chunks	3.861 GiB/s	12.890 GiB/s	+233.8%
Base64 forgiving MIME, 5.6 KiB	0.939 GiB/s	6.590 GiB/s	+602.0%
ASCII validation, 4 KiB	68.019 GiB/s	82.592 GiB/s	+21.4%
UTF-16 byte swap, 512 B	50.130 GiB/s	57.028 GiB/s	+13.8%
UTF-32 byte swap, 128 KiB	33.126 GiB/s	40.803 GiB/s	+23.2%
Base64 parallel, 4 threads, 16 KiB	0.266 GiB/s	6.995 GiB/s	+2531.6%