[OMNIML-5899] Add Q8_0 CUDA packing kernel - #2515
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Included review availability: This review used your included allowance. Your plan provides up to 12 included reviews per hour; 7 remain after this review. 📝 WalkthroughWalkthroughThe GGML CUDA extension now exposes ChangesQ8_0 packing
Priority: ⬇️ Low Estimated code review effort: 3 (Moderate) | ~20 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant PythonCaller
participant q8_0_pack
participant q8_0_pack_cuda
PythonCaller->>q8_0_pack: Submit input tensor
q8_0_pack->>q8_0_pack_cuda: Validate and pass contiguous input
q8_0_pack_cuda-->>q8_0_pack: Return packed tensor
q8_0_pack-->>PythonCaller: Return packed tensor
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✅ Passed checks (5 passed)
✨ Finishing Touches 💡 1📝 Generate docstrings 💡
🧪 Generate unit tests (beta)
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In `@tests/gpu/_extensions/test_torch_extensions.py`:
- Line 342: Update the per-block scale tensor d in the test so it has one
dimension before the later unsqueeze(1), keeping decoded aligned with its
corresponding weight rows rather than broadcasting across all rows.
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modelopt/torch/kernels/quantization/ggml/common.cuhmodelopt/torch/kernels/quantization/ggml/ggml.cppmodelopt/torch/kernels/quantization/ggml/q8_0.cumodelopt/torch/quantization/extensions.pytests/gpu/_extensions/test_torch_extensions.py
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Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
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Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
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/claude review |
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| AT_DISPATCH_FLOATING_TYPES_AND2( | ||
| at::ScalarType::Half, at::ScalarType::BFloat16, input.scalar_type(), "q8_0_pack", [&] { | ||
| encode<scalar_t><<<static_cast<int>(num_blocks), kQ8BlockSize, 0, stream>>>( |
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[SUGGESTION] One CUDA block per GGML block means 32 threads — a single warp — per block here, unlike the IQ kernels where the same convention yields a healthy kThreads == 256.
Impact: hardware caps resident blocks per SM (32 on Hopper/Ada), so 1 warp/block caps occupancy at ~50% of the warp slots, and a 4096×4096 tensor launches ~524k blocks each doing 5 dependent __shfl_down_sync ops. This is a streaming, bandwidth-bound kernel on a one-time export path, so the realistic cost is maybe 1.5–2x on this kernel rather than anything dramatic — hence a suggestion, not a blocker.
Suggestion: have each CUDA block encode kThreads / kQ8BlockSize == 8 GGML blocks, deriving block from blockIdx.x * (kThreads / kQ8BlockSize) + threadIdx.x / kQ8BlockSize and lane from threadIdx.x % kQ8BlockSize. The warp-level reduction and __shfl_sync broadcast already operate on exactly one warp, so they need no change — only the grid/block computation and the block >= num_blocks guard (which becomes live rather than dead) do. That also reuses the existing kThreads constant instead of implicitly picking a new block size.
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| module.def("q8_0_pack", &q8_0_pack, | ||
| "Pack a non-empty float32, float64, float16, or bfloat16 CUDA tensor whose innermost " | ||
| "dimension is a multiple of 32. Returns uint8 [numel / 32, 34] on the input device. " | ||
| "Non-finite input elements are treated as zero during packing, and finite elements " | ||
| "outside the float32 range saturate."); |
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[SUGGESTION] The documented saturation contract is incomplete for Q8_0.
q8_0.cu:46 clamps the scale to the fp16 maximum (d = fminf(amax / 127.0f, 65504.0f)), so any block whose amax exceeds 65504 * 127 ≈ 8.32e6 silently encodes at a scale smaller than the data requires, and every quant then saturates at ±127. Concretely, a block with amax == 1e8 — a perfectly ordinary finite float32 — dequantizes to 8.32e6, roughly a 12x underestimate, with no warning. That is a defensible choice (GGML's reference instead lets GGML_FP32_TO_FP16(d) overflow to +inf, which is strictly worse), but the docstring currently only promises that "finite elements outside the float32 range saturate", which reads as though in-range float32 values are always representable.
Since this docstring is the user-facing contract for the packer, consider stating the scale limit explicitly, e.g. "...blocks whose absolute maximum exceeds ~8.3e6 saturate, because the per-block scale is stored as float16." A matching note next to the 65504.0f clamp in q8_0.cu would help future readers too, since the bare literal doesn't explain why it is there.
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| at::Tensor q8_0_pack(at::Tensor input) { | ||
| TORCH_CHECK(input.is_cuda(), "Q8_0 packing requires a CUDA input"); | ||
| modelopt::ggml::check_scalar_pack_input("Q8_0", input, 32); |
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[SUGGESTION] The block size is a bare 32 here while the kernel's authority for it, kQ8BlockSize, lives in q8_0.cu's anonymous namespace and so cannot be referenced from this file.
This is exactly the drift the surrounding code takes pains to avoid: the IQ wrappers get kBlockSize from common.cuh, and the comment on check_pack_inputs explains that validation is shared so "the enforced rule and the message it reports are written once." With two independent literals, a future change to the Q8_0 block size in q8_0.cu leaves this wrapper validating the old value, and the mismatch surfaces as out-of-bounds writes rather than a TORCH_CHECK failure (the .cu entry point re-validates with its own constant, so the two checks would disagree silently).
Suggestion: move kQ8BlockSize (and ideally kPayloadBytes) into common.cuh next to kBlockSize / kScaleBytes, and use it in both places.
| kernels_ggml / "q8_0.cu", | ||
| ], | ||
| cuda_version_specifiers=">=11.8", | ||
| fail_msg="GGML IQ CUDA packing extension is unavailable.", |
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[SUGGESTION] The docstring above was deliberately de-IQ'd in this diff ("the GGML-compatible packing extension, exposing one packer per format"), but this user-facing failure message still says "IQ". A user who only requested Q8_0 packing now gets told the IQ extension is unavailable, which sends them looking in the wrong place.
Suggested change
| fail_msg="GGML IQ CUDA packing extension is unavailable.", | |
| fail_msg="GGML CUDA packing extension is unavailable.", |
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Claude review passed — no blocking issues found. LGTM
Scope: full review. All 5 changed files opened (144+/12-): q8_0.cu, common.cuh, ggml.cpp, extensions.py, and the GPU extension tests.
Findings
CRITICAL: 0 · IMPORTANT: 0 · SUGGESTION: 4
What I verified
The packer is faithful to GGML's quantize_row_q8_0_ref, which is the thing that actually matters for a format kernel:
- Byte layout —
kPayloadBytes = kScaleBytes + kQ8BlockSize == 34matchesblock_q8_0 { ggml_half d; int8_t qs[32]; }. The scale is written low-byte-first, so it is little-endian as GGML expects, and all 34 bytes of eachat::emptyrow are written (2 by lane 0, 32 by the warp) — no uninitialized output. - Scale/quant math —
d = amax / 127computed in fp32 and used in fp32 for the division, with the fp16 rounding only stored. This deliberately differs from the IQ kernels in the same directory, which quantize against__half2float(d_half), and the reference is the tiebreaker: llama.cpp also divides by the fp32d. Right call for bit-comparability against llama.cpp. - Rounding —
roundfis half-away-from-zero, matching the reference; the test's[127, 1, -1, 2, -2]expectation for[127, 0.5, -0.5, 1.5, -1.5]atd == 1.0pins this correctly. - Warp reduction — the 5-step
__shfl_down_syncleavesamaxvalid only in lane 0, which is exactly wheredis computed, and the__shfl_sync(..., 0)broadcast is reached by all 32 threads (the early return is block-uniform, so no divergent-shuffle hazard). - Zero blocks —
amax == 0yieldsd == 0, thed > 0.0fguard short-circuits the division, and the block encodes to 34 zero bytes. No division-by-zero, and the reference'sid = d ? 1/d : 0guard is preserved. - Non-finite contract — the docstring's "non-finite treated as zero" is backed by
load_floatincommon.cuh, which zeros non-finites and tests finiteness at source precision. NaNs are therefore excluded fromamaxrather than poisoning it. common.cuhrefactor — extractingcheck_scalar_pack_inputpreserves the IQ contract exactly; only the relative order of the grid-size check versus the codebook/device checks moves, which changes nothing but which message surfaces first.- Packaging —
pyproject.toml'spackage-datais a recursive**/*.cuglob, soq8_0.cuships in the wheel without a manifest edit. Dtype dispatch covers all four types the validator admits (AT_DISPATCH_FLOATING_TYPES_AND2→ float/double/half/bfloat16).
On the prior CodeRabbit finding
The comment on tests/gpu/_extensions/test_torch_extensions.py:342 claiming d needs a dimension before unsqueeze(1) does not hold. The weight is (4, 32), so each row is exactly one block: packed is (4, 34), packed[:, :2].view(torch.float16) is (4, 1), and .flatten() → unsqueeze(1) gives (4, 1), which broadcasts correctly against the (4, 32) quants. Rows stay aligned with their own scales. No change needed.
Suggestions (non-blocking)
- Launch config (
q8_0.cu:69) — 32 threads/block is one warp, capping occupancy near 50%; encoding 8 GGML blocks per 256-thread CUDA block would reuse the existingkThreads. Modest win on a one-time export path. - Saturation contract (
ggml.cpp:105) — the fp16 scale clamp means blocks withamax > ~8.3e6saturate silently; worth documenting, since the docstring currently only mentions the float32 range. - Duplicated block size (
ggml.cpp:77) — the bare32can drift fromkQ8BlockSize; promoting the constant tocommon.cuhmatches how the IQ wrappers sharekBlockSize. - Stale
fail_msg(extensions.py:103) — still says "IQ" after the extension became multi-family.
Risk
Low. Additive change: one new kernel, one new pybind entry, one new build source. No mode registration, no modelopt_state schema change, no public Python API change, and the only touched shared code (common.cuh) is a behavior-preserving extraction. Backward compatible. The suggestions are polish, not correctness.
One process note: the PR body still has the unfilled template ("Type of change: ?", empty Usage/Testing, unticked checklist) — worth filling the checklist boxes before merge, though the "Scoped change" and "Local checks" sections already cover the substance. As the description notes, the new CUDA tests need GPU CI; they were not runnable locally, so the kernel is reviewed-but-unexecuted here.
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Nudge: the kernel looks straightforward, but numerical edge coverage and CUDA execution evidence are incomplete.
Needs action:
- Add Q8_0 cases in
tests/gpu/_extensions/test_torch_extensions.pyfor float16/float64, NaN/Inf zeroing, finite float64 overflow, and fp16 scale saturation/underflow; verify packed bytes or decoded values. - Confirm GPU CI builds the shared GGML extension and passes the Q8_0 and existing IQ tests; the reported CPU-stack checks do not exercise this kernel.
- Confirm
q8_0.cureferences only GGML’s format, rather than adapting third-party implementation code; obtain human licensing sign-off if code was adapted.
No action needed:
- The new NVIDIA header matches
LICENSE_HEADER; existing test assertions are unchanged.
Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
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Addressed the actionable review items in 7d3f375: added Q8_0 extension coverage for float16/float64 byte parity, mixed NaN/Inf zeroing, finite float64 saturation, and FP16 scale saturation/underflow; documented that the CUDA implementation is independently written against the pinned GGML format and scalar formula. Human provenance sign-off has been requested from @NVIDIA/modelopt-setup-codeowners. GPU CI must still pass on this new head before the execution-evidence item is complete. |
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Nudge: numerical coverage and the scale-shape issue are resolved, but current-head CUDA execution evidence and requested human provenance confirmation remain pending.
Needs action:
- 💬 Author reports GPU CI is pending — provide a passing current-head run that builds the shared GGML extension and executes Q8_0 and existing IQ tests in
tests/gpu/_extensions/test_torch_extensions.py. - 💬 Author documents independent implementation and requested code-owner review — record human confirmation of
q8_0.cuprovenance and attribution before merge.
No action needed:
- ✔️ Resolved since the last review: dtype parity, non-finite handling, float64 overflow, FP16 scale saturation/underflow coverage, and per-block scale flattening.
- The NVIDIA header matches
LICENSE_HEADER; existing test assertions are preserved. Tests were inspected, not executed here. - Earlier launch-configuration, shared-constant, saturation-docstring, and failure-message suggestions remain non-blocking.
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### What does this PR do? Type of change: new feature **Second of two PRs adding IQ2_S** (2.5625 bits per weight). #2512 landed the PyTorch codec; this PR adds its **CUDA encoder** and makes the format reachable: - the CUDA encoder, its binding and extension build wiring, plus the CUDA path in `quantize_iq2_s` - an `IQFormat` record and **one `IQ_FORMAT_REGISTRY` entry**, so backend dispatch, both exporters and `convert_hf_config` take it from there - the `ggml` package export - the `general/ptq/iq2_s` recipe, its presets, `ptq.md` and a CHANGELOG entry The kernel lands with the registration so every registered format keeps a CUDA encoder. On the mixed-precision checkpoint #2511 measured (`unsloth/Qwen3.8-27B-GGUF`), IQ2_S covers **9 tensors and 0.6 B parameters**. ### The kernel IQ2_S's **1024-entry codebook is twice IQ2_XS's**, which makes its search the most expensive in the family. The codebook and its norms take 36 KiB of shared memory, the most of any IQ kernel but inside the 48 KiB static limit, so they are declared statically like the IQ2_XS and IQ2_XXS kernels. That cost is why the kernel matters more here than anywhere else: | | torch | CUDA | | |---|---|---|---| | IQ2_S, 5632×2048 weight | 0.8 M elem/s | **725.7 M elem/s** | **907×** | | extrapolated to a 27B model | ~9.8 hours | **~37 s** | | ### Usage ```bash python examples/hf_ptq/hf_ptq.py --pyt_ckpt_path <model> --recipe general/ptq/iq2_s ``` ### Testing Registering the format brings it under every registry-driven test with no IQ2_S-specific test code: backend dispatch and weight caching, the `num_bits` guard, `convert_hf_config` metadata (uniform and mixed precision), all 9 Megatron export tests, and the two `TensorQuantizer` tests in the shared battery. The shared CUDA battery gains one row. - `tests/unit/torch/quantization/test_ggml_backend.py`, `test_iq_formats.py`, `tests/unit/torch/export/test_convert_hf_config.py`, `tests/unit/recipe/test_presets.py`: **134 passed** - broader unit sweep (`-k 'ggml or iq or gguf or registry'` over quantization, export and recipe tests): **192 passed**. The one failure, `test_export_registry.py::test_builtin_dispatch_covers_all_handler_shapes`, is a `torchvision` import error in my environment, unrelated to IQ. - `tests/gpu/torch/quantization/test_iq_formats_cuda.py`, `test_iq1_s_cuda.py`, `test_iq2_xs_cuda.py`: **42 passed** on RTX PRO 6000 Blackwell (sm_120). 7 of them are IQ2_S: CUDA-vs-PyTorch encoder parity, determinism, reconstruction at scale, zero and non-finite policy, float64 input and the fallback path. - `tests/gpu_megatron/torch/export/test_unified_export_megatron.py -k 'iq or ggml'`: **36 passed** (9 tests × 4 formats) in `nvcr.io/nvidia/nemo:26.08` - `tests/examples/hf_ptq/test_llm_ptq.py -k iq2_s`: **passed**. TinyLlama PTQ through unified HF export writes `quant_algo: IQ2_S`, `block_payload_bytes: 82`, and `down_proj` packed as `(2048, 22, 82)` uint8. - `general/ptq` now holds 30 recipes. - The shared-memory change in `b7739d5d0` leaves the packed bytes identical (same hash on a 5632×2048 weight), and packing runs at 849.1 M elem/s against 825.7 before on RTX PRO 6000. The GPU battery was rerun: 42 passed. All of the above was rerun after rebasing onto `main` at `c2aaa44f6`. That base adds a Q8_0 packer to the same GGML extension (#2515), and changes the hf_ptq example and the export code this format goes through. The packed IQ2_S bytes still hash the same. On this RTX PRO 6000 (sm_120), two of #2515's own Q8_0 tests in `tests/gpu/_extensions/test_torch_extensions.py` fail: `test_cuda_ext_q8_0_zero_and_roundf_layout` and `test_cuda_ext_q8_0_dequantizes_with_small_error`. They fail identically on a clean `main` checkout, so they are not from this PR. ### Before your PR is "*Ready for review*" - Is this change backward compatible?: ✅ - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`: ✅ No new code sources or dependencies. - Did you write any new necessary tests?: ✅ - Did you update Changelog?: ✅ - Did you get Claude approval on this PR?: ❌ Not yet run. ### Additional Information Merge order: #2511 (IQ2_XXS, merged) → #2525 (format registry, merged) → #2512 (IQ2_S codec, merged) → **this** → #2513 (IQ1_M). 🤖 Generated with [Claude Code](https://claude.com/claude-code) <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **New Features** * Added IQ2_S weight-only quantization for eligible linear layers, at 2.5625 bits per weight. * Added a PTQ recipe that requires no calibration data. Weights must meet the existing 256-value block-size constraint. * Added CUDA-accelerated packing for CUDA weights, with a Python fallback when the CUDA extension is unavailable. * **Documentation** * Updated the PTQ recipe catalog and IQ-format size tradeoffs. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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### What does this PR do? Type of change: new feature **Second of two PRs adding IQ1_M** (1.75 bits per weight). #2513 landed the PyTorch codec; this PR adds its **CUDA encoder** and makes the format reachable. With it, ModelOpt supports all five GGML IQ formats at one and two bits. - the CUDA encoder, its binding and extension build wiring, plus the CUDA path in `quantize_iq1_m` - an `IQFormat` record and **one `IQ_FORMAT_REGISTRY` entry**, so backend dispatch, both exporters and `convert_hf_config` take it from there - the `ggml` package export - the `general/ptq/iq1_m` recipe, its presets, `ptq.md` and a CHANGELOG entry The kernel lands with the registration so every registered format keeps a CUDA encoder. ### The kernel In the kernel the delta shift is free per group, so it sits above the entry index in the sort key: a tie still prefers the lower shift and then the lower entry, as the reference encoder does. The 2048-entry grid IQ1_M shares with IQ1_S is 64 KiB, past the 48 KiB static shared-memory limit, so both kernels read it from global memory and rely on the cache. | 5632×2048 weight | torch | CUDA | | |---|---|---|---| | IQ1_M encode | 5.6 M elem/s | **318 M elem/s** | **57×** | ### Shared with IQ1_S rather than copied The two IQ1 kernels load each vector, score it against a grid entry and apply the ±1/8 shift the same way. So those three steps move into `common.cuh` as `load_vector`, `grid_terms` and `shifted_error`, and IQ1_S uses them too. **IQ1_S's packed bytes are unchanged**: its CUDA output on a 5632×2048 weight hashes the same before and after, and so does IQ1_M's, compared against the pre-split version of this change. IQ1_S encodes at the same speed (306 M elem/s). ### Usage ```bash python examples/hf_ptq/hf_ptq.py --pyt_ckpt_path <model> --recipe general/ptq/iq1_m ``` ### Testing Registering the format brings it under every registry-driven test with no IQ1_M-specific test code: backend dispatch, weight caching, the `num_bits` guard, `convert_hf_config` metadata, Megatron export and the `TensorQuantizer` tests in the shared battery. The shared CUDA battery gains one row. - `tests/unit/torch/quantization/test_ggml_backend.py`, `test_iq_formats.py`, `tests/unit/torch/export/test_convert_hf_config.py`, `tests/unit/recipe/test_presets.py`: **166 passed** - broader unit sweep (`-k 'ggml or iq or gguf or registry'` over quantization, export and recipe tests): **221 passed**. The one failure, `test_export_registry.py::test_builtin_dispatch_covers_all_handler_shapes`, is a `torchvision` import error in my environment, unrelated to IQ. - `tests/gpu/torch/quantization/test_iq_formats_cuda.py`, `test_iq1_s_cuda.py`, `test_iq2_xs_cuda.py`: **49 passed** on RTX PRO 6000 Blackwell (sm_120), 7 of them IQ1_M, including CUDA-vs-PyTorch encoder parity - `tests/gpu_megatron/torch/export/test_unified_export_megatron.py -k 'iq or ggml'`: **45 passed** (9 tests × 5 formats) in `nvcr.io/nvidia/nemo:26.08` - `tests/examples/hf_ptq/test_llm_ptq.py -k iq1_m`: **passed** - reconstruction error falls monotonically across all five formats, pinned by a test - `general/ptq` now holds 31 recipes; `ptq.md` is updated. Rebased onto `main` after #2513 merged. The resulting tree is identical to the one the runs above tested, and the unit set was rerun on it: 166 passed. On this GPU, two of #2515's Q8_0 tests in `tests/gpu/_extensions/test_torch_extensions.py` fail: `test_cuda_ext_q8_0_zero_and_roundf_layout` and `test_cuda_ext_q8_0_dequantizes_with_small_error`. They fail identically on a clean `main` checkout, so they are not from this PR. ### Before your PR is "*Ready for review*" - Is this change backward compatible?: ✅ - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`: ✅ No new code sources or dependencies. - Did you write any new necessary tests?: ✅ - Did you update Changelog?: ✅ - Did you get Claude approval on this PR?: ❌ Not yet run. ### Additional Information Merge order: #2511 (IQ2_XXS) → #2525 (format registry) → #2512 (IQ2_S codec) → #2565 (IQ2_S CUDA encoder and registration) → #2513 (IQ1_M codec), all merged → **this**. 🤖 Generated with [Claude Code](https://claude.com/claude-code) <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **New Features** * Added IQ1_M weight-only quantization at 1.75 bits per weight, with CUDA acceleration and a 256-value block size. * Added an IQ1_M post-training quantization recipe for eligible linear layers; calibration data is not required. * Added IQ1_M to the supported GGML-compatible formats and recipe listings. <!-- end of auto-generated comment: release notes by coderabbit.ai --> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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### What does this PR do? Type of change: refactor (no behaviour change) The five GGML IQ CUDA encoders were five copies of the same search. IQ2_XS and IQ2_XXS shared 139 of their roughly 150 lines of encoder and launcher code, and IQ2_S 113 of them. IQ1_S and IQ1_M had the same structure with a different choice space. Every scaled packer also validated its scales twice, in the `ggml.cpp` pybind wrapper and again in the CUDA entry point. This PR keeps **one encoder per family**, as two templates: - **`iq2_family.cuh`** for IQ2_XS, IQ2_XXS and IQ2_S. The grid sits in shared memory, the 16 local scales are scored per group, and each vector then takes its best entry under the chosen scale. A format supplies its group shape, whether it stores seven sign bits and recovers the eighth from parity, and a `store()` that writes the chosen entries, sign masks and local scales into its layout. - **`iq1_family.cuh`** for IQ1_S and IQ1_M, over the shared ternary grid. Each group picks one of `kChoices` options. With `kSharedShift` the option also fixes the ±1/8 delta (IQ1_S: `shift * 8 + local`); otherwise each vector picks its own (IQ1_M). IQ1_S's scale kernel now writes FP16 scales, so both IQ1 formats take the same input. Each format file is now one `Format` struct, holding its layout constants and `store()`, plus its entry point: 58–100 lines each. Validation lives once in `common.cuh`, as `check_pack_inputs` and `check_scaled_pack_inputs`. `ggml.cpp` binds the CUDA entry points directly instead of through five wrappers. **The kernel sources shrink from 1,536 to 1,241 lines** (+665 / −960). This is the first of two PRs. #2604 builds on it: it adds CUDA decoders as a `decode()` next to each format's `store()`, and makes export reuse fake quant's packed payloads. ### Testing **Nothing changes in the output.** Before the refactor I hashed 40 outputs: 5 formats × float32/bfloat16/float16/float64 inputs × encode and decode, on a weight with zero, tiny, oversized and non-finite blocks. All 40 hash the same afterwards. **Encode speed is unchanged.** Old and new were timed alternately for four rounds, in both orders, on an idle RTX PRO 6000 with a 5632×2048 weight. They were within 1% for every format: IQ1_S 37.6 / 37.6 ms, IQ1_M 37.0 / 37.0, IQ2_XXS 10.9 / 10.9, IQ2_XS 11.9 / 12.0, IQ2_S 15.5 / 15.4. - `tests/gpu/torch/quantization/test_iq_formats_cuda.py`, `test_iq1_s_cuda.py`, `test_iq2_xs_cuda.py`: **49 passed** - **Validation reports the same errors in the same order.** Over 5 formats × 8 combinations of bad arguments (devices, dtype, width, grid shape, scales dtype, length and sign), every first error matches main's. - `tests/gpu/_extensions/test_torch_extensions.py`: the validation-message tests pass. #2515's two Q8_0 tests fail identically on a clean `main` on this GPU. - IQ unit tests (`test_ggml_backend.py`, `test_iq_formats.py`, `test_convert_hf_config.py`, `test_presets.py`, `test_export_weight.py`): **173 passed** ### Before your PR is "*Ready for review*" - Is this change backward compatible?: ✅ Same bindings, messages and bytes. - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`: ✅ No new code sources or dependencies. - Did you write any new necessary tests?: N/A. A refactor with no behaviour change, verified by the hashes above and the existing GPU tests. - Did you update Changelog?: N/A - Did you get Claude approval on this PR?: ❌ Not yet run. ### Additional Information Merge order: **this** → #2604 (pack each IQ weight once and decode on CUDA). 🤖 Generated with [Claude Code](https://claude.com/claude-code) <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **Bug Fixes** * Quantization now checks that inputs and grids are CUDA tensors on the same device, with compatible shapes. Scaled formats also validate scale type, shape, and finite, non-negative values. * **Improvements** * IQ1 and IQ2 formats share common encoding paths while retaining their format-specific output layouts. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
cjluo-nv
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Oct 2, 2026
### What does this PR do? Type of change: performance Two fixes that make fake-quantized GGML IQ models fast. Both were found by instrumenting the hf_ptq example (TinyLlama, 154 IQ weights, 100-token preview) and counting every encode and decode per weight. 1. **Each weight is packed once.** Fake quant packs a weight on its first forward and caches the payload, but export then ran the search again on the same unchanged weight: 154 more encodes for 154 weights, in all five formats. `IQFormat.pack` now reuses the cached payload when it was packed from the weight being exported, so the checkpoint also holds exactly the bytes the evaluated model decoded. 2. **Decoding runs on CUDA.** All five formats had CUDA encoders but decoded with PyTorch ops. Fake quant decodes every weight on every forward, so once packing was fast and cached, decoding was **55–66% of the run**, about 3 ms per weight per forward; on a 27B model that is about 10 s per forward. Each format's `Format` struct from #2615 gains a bit-exact `decode()` beside its `store()`. ### Results The instrumented hf_ptq example on the same GPU, with the extension already built: | format | total wall before → after | encodes at export | decode time before → after | |---|---|---|---| | IQ1_S | 55.6 → **21.9 s** | 154 → **0** | 32.0 → **1.4 s** | | IQ1_M | 69.8 → **21.0 s** | 154 → **0** | 46.3 → **1.3 s** | | IQ2_XXS | 61.6 → **19.0 s** | 154 → **0** | 41.9 → **1.3 s** | | IQ2_XS | 63.8 → **19.1 s** | 154 → **0** | 44.3 → **1.3 s** | | IQ2_S | 55.6 → **19.9 s** | 154 → **0** | 35.8 → **1.3 s** | Fake quant still packs each weight exactly once and decodes it 100 times, once per preview token. IQ1_M was the slowest format before because its PyTorch decoder did the most work; it now matches IQ1_S. Decoding one 5632×2048 weight goes from 3.3–5.2 ms to **0.06–0.14 ms**. ### How **Reusing the payload.** TensorQuantizer hands fake quant the weight reshaped into 256-value blocks, so the cache is keyed on that view, while export holds the weight itself. An exact-key match therefore never hit in a real model, even though a 256-wide unit test passed. `pack` also accepts another contiguous view of the same storage, version and length: the same values in the same order, hence the same GGML blocks. It then reshapes the payload to the weight's layout. The version counter still makes a weight edited after its forward pack afresh. The Megatron exporter keeps packing on its own, since it can remap or slice a weight before packing it. **Bit-exact decoders.** One CUDA thread decodes one 8-value vector. Every float operation is explicitly rounded (`__fmul_rn`, `__fadd_rn`, `__fdiv_rn`) in the PyTorch decoder's order, so the compiler cannot fuse a multiply into an add, and the output is bit-identical to the PyTorch decoders. `dequantize_<format>` uses the unpacker for CUDA payloads and keeps the PyTorch path otherwise. ### Testing - `tests/gpu/torch/quantization/test_iq_formats_cuda.py`, `test_iq1_s_cuda.py`, `test_iq2_xs_cuda.py`: **74 passed** on RTX PRO 6000 (sm_120). That includes 25 new decoder cases: for each format, CUDA equals the PyTorch decoder bit for bit in four dtypes, on random payloads (including block scales that decode to inf or NaN) and real encodings. The CUDA path also reproduces llama.cpp's values on the conformance blocks. Dropping IQ2_XXS's parity bit in the kernel fails all five IQ2_XXS cases. - `tests/unit/torch/export/test_export_weight.py`: export reuses the cached payload without calling the encoder, and repacks a weight edited after its forward, for all five formats. The weight is 512 wide so the blocked view really differs; with an exact-key match only, the reuse test fails for every format. The IQ payload export test covers all five formats rather than two. - IQ unit tests (`test_ggml_backend.py`, `test_iq_formats.py`, `test_convert_hf_config.py`, `test_presets.py`, `test_export_weight.py`): **186 passed** - `tests/gpu_megatron/torch/export/test_unified_export_megatron.py -k 'iq or ggml'`: **45 passed** in `nvcr.io/nvidia/nemo:26.08` - `tests/examples/hf_ptq/test_llm_ptq.py -k iq`: **5 passed**, 27.7–30.9 s each - On this GPU, `test_torch_extensions.py` still shows #2515's two Q8_0 failures, which fail identically on a clean `main`. ### Before your PR is "*Ready for review*" - Is this change backward compatible?: ✅ Same bindings, error messages, exported bytes and decoded values, only faster. - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`: ✅ No new code sources or dependencies. - Did you write any new necessary tests?: ✅ - Did you update Changelog?: N/A. It speeds up formats added in this unreleased cycle without changing their output. - Did you get Claude approval on this PR?: ❌ Not yet run. ### Additional Information Builds on #2615 (one CUDA encoder per IQ family), now merged. Follows the IQ series (#2511, #2525, #2512, #2565, #2513, #2595), all merged. The benchmark above was measured on the combined branch before the split. After rebasing onto `main` with #2615 merged, this PR's code is the same apart from `kVectorsPerBlock` moving into `common.cuh`'s shared constants and #2615's validation-order fix. On the rebased branch, all 40 encoder and decoder hashes match, 74 GPU tests pass and 186 unit tests pass. 🤖 Generated with [Claude Code](https://claude.com/claude-code) --------- Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
hychiang-git
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Oct 2, 2026
### What does this PR do? Type of change: new feature Adds Q8_0 encoding, decoding, and the GGML fake-quant backend. Each 32-weight block stores one FP16 scale and 32 signed int8 values in 34 bytes (8.5 bits per weight). - Generalizes dispatch to `GGML_FORMAT_REGISTRY` / `GGMLFormat` while preserving `IQFormat` as a type alias. `IQ_FORMAT_REGISTRY` is an IQ-only compatibility dictionary sharing the same format records, not a mutation-propagating view. - Retains IQ1_S, IQ1_M, IQ2_XXS, IQ2_XS, and IQ2_S registrations alongside Q8_0. - Uses the merged `q8_0_pack` CUDA extension when available and the PyTorch encoder otherwise. - Matches canonical reciprocal-then-multiply rounding, using the unrounded FP32 scale to choose int8 values and FP16 only for serialized scale storage. - Adds exact-byte rounding regressions and checks that the compatibility registry shares the same format records. Removes a redundant zero-block buffer copy. Checkpoint export, recipes, documentation, and the user-facing Q8_0 changelog remain in #2517. ### Base and dependencies The target remains `main`. Current head `71e3183a7b7eac7e5e3888ee45a206c572028af9` includes main at `67a68f8fd4902a7b67c78a2f00f40562b081fe72`, including #2595 (IQ1_M registration), #2615 (shared IQ CUDA encoders), and #2604 (packed-weight cache reuse and CUDA IQ decoding). All five IQ formats, Q8_0, and the compatibility aliases are retained. The comparison against `main` contains only the intended 12 Q8_0 files, with 207 added source lines excluding tests and docs. The inherited IQ refactor and export changes are not part of this PR's diff. #2515 has already merged and supplies the Q8_0 kernel. This PR retains the small reciprocal-rounding correction to that kernel needed for exact reference parity. ### Usage ```python import torch from modelopt.torch.quantization.ggml import quantize_q8_0, dequantize_q8_0 weight = torch.randn(2, 64, dtype=torch.bfloat16) packed, shape = quantize_q8_0(weight) restored = dequantize_q8_0(packed, shape) ``` The final weight dimension must be divisible by 32. Backend dispatch also accepts `num_bits="q8_0"`, `backend="ggml"`, and `block_sizes={-1: 32}`. ### Testing - Current head `71e3183a7`: **183 focused CPU tests passed**, covering Q8_0, all six registered backends, IQ formats, export metadata, and recipe presets. - Current-head applicable pre-commit checks passed: Ruff, formatting, mypy, CUDA formatting, license headers, security checks, merge markers, line endings, and file size. - Previous head `2beb70ffa`: **all six Q8_0 CUDA cases passed**, including exact-byte reciprocal rounding and unrounded-scale regressions; [GPU job log](https://github.com/NVIDIA/Model-Optimizer/actions/runs/36890153545/job/110468900810). That GPU lane completed with 1,663 passed and 67 skipped. The overall workflow was cancelled after a different lane was cancelled; it is not an all-green workflow result. - Current head `71e3183a7`: the GPU CI mirror now points to the exact PR head. [GPU CI](https://github.com/NVIDIA/Model-Optimizer/actions/runs/37061248628), [example CI](https://github.com/NVIDIA/Model-Optimizer/actions/runs/37061248555), and [regression CI](https://github.com/NVIDIA/Model-Optimizer/actions/runs/37061248637) are running. Previous-head results do not validate this new head. ### Before your PR is "*Ready for review*" - Is this change backward compatible?: yes; existing IQ names and registrations are retained. - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`?: yes; no new dependency. - Did you write any new necessary tests?: yes. - Did you update `CHANGELOG.rst`?: N/A here; #2517 carries the single Q8_0 feature entry. - Did you get Claude approval on this PR?: pending current-head review. ### Related PRs 1. [#2515 — Q8_0 CUDA packing kernel](#2515) — merged. 2. [#2595 — IQ1_M registration](#2595) — merged. 3. **#2516 — Q8_0 quantization codec and backend** — this PR. 4. [#2517 — Q8_0 checkpoint export and recipes](#2517) — follows this PR. <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **New Features** * Added Q8_0 quantization support, including weight packing, unpacking, and fake quantization. * Added Q8_0 to the available GGML formats, alongside existing IQ formats, through a shared quantization interface. * Added support for formats with different block sizes when validating weights. * Q8_0 uses CUDA acceleration when available and falls back to PyTorch when needed. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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What does this PR do?
Type of change: new feature
Adds the Q8_0 CUDA packing layer for the three-PR Q8_0 series:
q8_0_packthrough the shared GGML extension;This PR contains only the kernel and extension boundary. The codec/backend and export/recipe layers remain in the later PRs.
Usage
Testing
Before your PR is "Ready for review"
CONTRIBUTING.md: yes; no dependency was added and no implementation code was copiedCHANGELOG.rst?: N/A; the user-facing entry is in [OMNIML-5899] Export Q8_0 checkpoints and add recipes #2517Provenance
The CUDA encoder was independently written for ModelOpt. It implements the packed-format contract and scalar quantization formula documented by the pinned llama.cpp definitions:
No llama.cpp implementation code is incorporated into this CUDA source. Human code-owner confirmation of this provenance and attribution is requested before merge.
Related PRs
Merge order:
All three PRs target
main.