[voltjia]

Summary

• Add MetaX vLLM rms_norm as linked implementation slot 16.
• Add shared TorchRmsNorm<Backend> handling tensor conversion, contiguous staging, stream guards, and output copy-back.
• Extend tests/test_rms_norm.py with a non-default stream case.

Motivation

The first linked-operator PR validates one silu_and_mul implementation across providers. This PR checks that the same architecture also supports a structurally different operator with two input tensors, a scalar attribute, and explicit output mapping.

InfiniOps keeps rms_norm(input, weight, eps, out). The installed MetaX vLLM DSO is verified by both nm -D -C and readelf to export:

void rms_norm(at::Tensor& out, at::Tensor& input,
              at::Tensor& weight, double epsilon);

Depends on #876. N/A - no linked issue.

Type of Change

• feat - new feature / new operator / new platform
• fix - bug fix
• perf - performance improvement (no behavioral change)
• refactor - code restructuring without behavior change
• test - adding or fixing tests only
• docs - documentation only
• build / ci - build system or CI configuration
• chore - tooling, formatting, or other non-code changes
• Breaking change

Platforms Affected

• CPU (WITH_CPU)
• NVIDIA (WITH_NVIDIA)
• Iluvatar (WITH_ILUVATAR)
• MetaX (WITH_METAX)
• Cambricon (WITH_CAMBRICON)
• Moore (WITH_MOORE)
• Ascend (WITH_ASCEND)
• PyTorch C++ bindings (WITH_TORCH)
• Build system / CMake / CI
• Python bindings / user-facing API

Smoke Test Result

Pending: operator-pruned MetaX linked build, tests/test_rms_norm.py, and the existing smoke set.
The source upload to the MetaX validation host requires explicit authorization.

Test Results on Supported Platforms

Platform	Affected	Build / Smoke Result	Full Result / Notes
NVIDIA	No	N/A - not affected	Host-independent clang-format/Ruff checks only
Iluvatar	No	N/A - not affected	N/A
MetaX	Yes	Pending remote linked build	Exported ABI verified in the pinned vLLM DSO
Cambricon	No	N/A - not affected	Separate draft PR
Moore	No	N/A - not affected	Separate draft PR
Ascend	No	N/A - not affected	N/A

Static validation

clang-format 21 --dry-run --Werror <changed C++ files>
exit 0
ruff 0.15.22 format --check tests/test_rms_norm.py
1 file already formatted
ruff 0.15.22 check tests/test_rms_norm.py
All checks passed!
git diff --cached --check
exit 0

Benchmark / Performance Impact

N/A - this PR validates linked integration correctness and makes no performance claim.

Notes for Reviewers

• TorchRmsNorm<Backend> owns layout staging and copy-back; VllmRmsNorm::Call owns only the exact external ABI.
• The output-last InfiniOps convention is preserved even though the provider ABI takes out first.
• The implementation reuses the vLLM DSO and C10<Device::Type::kMetax> introduced by feat(linked): add MetaX vLLM silu_and_mul backend #873.
• This is the fifth PR in the linked-operator stack and depends on feat(cambricon): link Apex silu_and_mul #876.