diff --git a/security-monitor/src/core/architecture/riscv/mmu/page_table.rs b/security-monitor/src/core/architecture/riscv/mmu/page_table.rs index b41d1c8..a0f4472 100644 --- a/security-monitor/src/core/architecture/riscv/mmu/page_table.rs +++ b/security-monitor/src/core/architecture/riscv/mmu/page_table.rs @@ -127,7 +127,7 @@ impl PageTable { let address = NonConfidentialMemoryAddress::new(pointer)?; let page_size = paging_system.data_page_size(level); let page = PageAllocator::acquire_page(page_size)?.copy_from_non_confidential_memory(address)?; - LogicalPageTableEntry::PageWithConfidentialVmData(Box::new(page)) + LogicalPageTableEntry::PageWithConfidentialVmData(page) } }; serialized_representation.write(index, logical_page_table_entry.serialize()).unwrap(); @@ -161,7 +161,7 @@ impl PageTable { &mut self, confidential_vm_address: &ConfidentialVmPhysicalAddress, page_size: &PageSize, ) -> Result { let page = PageAllocator::acquire_page(*page_size)?.zeroize(); - let entry = LogicalPageTableEntry::PageWithConfidentialVmData(Box::new(page)); + let entry = LogicalPageTableEntry::PageWithConfidentialVmData(page); self.map_page(confidential_vm_address, page_size, entry)?; Ok(*page_size) } diff --git a/security-monitor/src/core/architecture/riscv/mmu/page_table_entry.rs b/security-monitor/src/core/architecture/riscv/mmu/page_table_entry.rs index 4442ab9..770bb11 100644 --- a/security-monitor/src/core/architecture/riscv/mmu/page_table_entry.rs +++ b/security-monitor/src/core/architecture/riscv/mmu/page_table_entry.rs @@ -19,7 +19,7 @@ pub(super) enum LogicalPageTableEntry { PointerToNextPageTable(Box), #[rr::pattern("PageWithConfidentialVmData" $ "p", "conf", "perm")] #[rr::refinement("-[ #(#p); #conf; #perm]")] - PageWithConfidentialVmData(Box>), + PageWithConfidentialVmData(Page), #[rr::pattern("PageSharedWithHypervisor" $ "sp", "conf", "perm")] #[rr::refinement("-[ #sp; #conf; #perm]")] PageSharedWithHypervisor(SharedPage),